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"excerpt": "Frequency synthesis is an electronic design technique that generates signals at desired frequencies from one or more reference oscillators, using phase-locked loops, direct digital synthesis, and related loop-based architectures.",
"snippet": "Frequency synthesis is an electronic design technique that generates signals at desired frequencies from one or more reference oscillators, using phase-locked loops, direct digital synthesis, and related loop-based architectures.",
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"markdown": "# Frequency synthesis\n\nFrequency synthesis is an electronic design technique that generates signals at desired frequencies from one or more reference oscillators, using techniques such as phase-locked loops (PLLs) and direct digital synthesis (DDS). The 2023 tutorial by Alexander Chenakin, a synthesizer designer and author of microwave frequency-synthesis references, groups the main architectures into direct analog, direct digital, and indirect (loop-based) synthesis, with fractional-N, DDS, frequency-offset, and multiloop schemes as the principal building blocks.[1](https://doi.org/10.1109/mmm.2023.3265464) Loop synthesis is generally preferred for spectral purity, while DDS is generally preferred for switching speed, phase continuity, and fine resolution.[2](https://www.am1.us/wp-content/uploads/2017/11/Advanced-Phase-Lock-Applications-Synthesis-Ch5-V1.1.pdf)\n\n| Key fact | Value | Condition |\n|---|---|---|\n| PLL phase-noise penalty from division ratio | 20·log(N) degradation | Multiplying a 100 kHz crystal to 1000 MHz (N = 10,000) costs 80 dB[3](https://www.ti.com/lit/an/swra029/swra029.pdf) |\n| DDS tuning equation | \\( f_{\\mathrm{out}} = M \\cdot f_{c}/2^{n} \\) | n typically 24–32 accumulator bits[4](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf) |\n| DDS frequency resolution | \\( f_{c}/2^{n} \\) | For n = 32, better than one part in four billion[4](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf) |\n| DDS practical maximum output | About one-third of the clock frequency | Nyquist limit is one-half; filtering and DAC set the practical bound[4](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf) |\n| Delta-sigma fractional-N divider range | Up to 2ⁿ values for an nth-order modulator | Third order: 8 values; fourth order: 16 |\n| Commercial integer-N floor (ADF41513) | −235 dBc/Hz normalized | Integer-N mode, 1 MHz loop bandwidth[5](https://www.analog.com/media/en/technical-documentation/data-sheets/adf41513.pdf) |\n| Best recent integrated jitter | 33.8 fs rms | 14 GHz chopper-refolding sampling PLL, 28 nm CMOS[6](https://doi.org/10.1109/isscc49663.2026.11409284) |\n\n## How it works\n\nA PLL is a feedback system containing a voltage-controlled oscillator (VCO), a phase detector, and a low-pass loop filter; in lock it forces the VCO to track the frequency and phase of the input.[7](https://web.ece.ucsb.edu/~long/ece145b/PLL_intro_FMD_FS.pdf) Placing a divider by N in the feedback path makes the VCO run at N times the reference frequency. The cost is noise: reference phase-noise power at the output is multiplied by \\( N^{2} \\), a 20·log(N) penalty for offsets inside the loop bandwidth.[7](https://web.ece.ucsb.edu/~long/ece145b/PLL_intro_FMD_FS.pdf)\n\nDDS works differently. An n-bit phase accumulator advances by a tuning word M every clock cycle, and a sine lookup table plus DAC converts the accumulated phase to a waveform, giving \\( f_{\\mathrm{out}} = M \\cdot f_{c}/2^{n} \\) and resolution \\( f_{c}/2^{n} \\).[4](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf) Changing M shifts the frequency instantaneously with no phase discontinuity.[4](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf)\n\n## How it is done\n\nA PLL synthesizer design starts from the channel plan. The phase-detector frequency is a design choice bounded by the frequency plan: in an integer-N loop it cannot exceed the channel spacing, the greatest common divisor of the channel frequencies, while a fractional-N loop can use a higher phase-detector frequency.[23](https://www.ti.com/lit/pdf/snap003) The N divider is built from a dual-modulus prescaler (for example 32/33) plus A and B counters. Loop stability requires at least 40–45 degrees of phase margin at the unity-gain frequency, and to attenuate reference spurs by 40 dB the crossover frequency must sit a factor of 100 below the reference frequency.[3](https://www.ti.com/lit/an/swra029/swra029.pdf) • [7](https://web.ece.ucsb.edu/~long/ece145b/PLL_intro_FMD_FS.pdf)\n\nFor a DDS, the designer chooses the accumulator width (24–32 bits), truncates the phase to roughly 13–15 most significant bits before table lookup, and decides on dithering.[4](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf)\n\n## Origin\n\nThe term and the problem trace to H.J. Finden's 1943 paper \"The frequency synthesizer\" in the Journal of the Institution of Electrical Engineers.[8](https://doi.org/10.1049/ji-3-1.1943.0031) Earlier loop-synthesis theory built on Gaston Salmet's 1956 analysis of pulse-synchronized oscillators in the Proceedings of the IRE[9](https://doi.org/10.1109/jrproc.1956.274877) and B.M. Wojciechowski's 1960 \"Theory of a Frequency-Synthesizing Network\" in the Bell System Technical Journal.[10](https://doi.org/10.1002/j.1538-7305.1960.tb03937.x) A transistorized PLL synthesizer provided 30,000 discrete frequencies between 2 and 32 Mc/s in 1 kc/s steps with the stability of the driving frequency standard.[11](https://doi.org/10.1049/jbire.1961.0044) J. Noordanus of Philips surveyed the field in 1969 and concluded that loop systems were very attractive for spectral purity, electronic tuning, solid-state design, and microminiaturization.[12](https://doi.org/10.1109/tcom.1969.1090079) A patent covered synthesizing \\( f_{2} = (M/N) \\cdot f_{1} \\) by modulo-M accumulation.[13](https://www.freepatentsonline.com/4145667.html) Direct digital synthesis came to the forefront as a viable method and was popularized by a 1975 IEEE publication; the original 1971 paper is not identified in the published accounts.[2](https://www.am1.us/wp-content/uploads/2017/11/Advanced-Phase-Lock-Applications-Synthesis-Ch5-V1.1.pdf) Venceslav F. Kroupa's 1998 volume collected the DDS literature.[14](https://doi.org/10.1109/9780470544396)\n\n## Variants\n\n**Integer-N.** With an integer divider, the minimum step size equals the reference frequency, so fine steps force a low reference, which is often undesirable.[15](https://api.pageplace.de/preview/DT0400.9781580539838_A25416332/preview-9781580539838_A25416332.pdf)\n\n**Fractional-N.** The loop division ratio is swapped between integers so the average is fractional, allowing a high reference frequency with fine step size, lower in-band phase noise, and faster transient response.[15](https://api.pageplace.de/preview/DT0400.9781580539838_A25416332/preview-9781580539838_A25416332.pdf) Traditional designs alternate the N counter between two values, but the periodic sequence produces spurs.\n\n**Delta-sigma (MASH) fractional-N.** The 1993 paper by T.A.D. Riley, M.A. Copeland, and T. Kwaśniewski showed that the pulse-swallowing method is equivalent to a first-order delta-sigma modulated dual-modulus divider, that first-order modulation fails to randomize quantization error, and that higher-order modulation noise-shapes the divider jitter.[16](https://ewh.ieee.org/r5/denver/sscs/References/1993_05_Riley.pdf) An nth-order modulator switches the N counter among up to 2ⁿ values, and the MASH (Multi-stAge noise SHaping) structure is a common implementation; dithering reduces sub-fractional spurs.\n\n**All-digital and sub-sampling PLLs.** All-digital PLLs divide into divider-based designs, where a digitally controlled oscillator replaces the VCO and a time-to-digital converter replaces the phase detector and charge pump, and divider-less designs such as sub-sampling, accumulator-based, and injection-locked loops.[17](https://www.mdpi.com/2072-666X/16/3/333) Sub-sampling PLLs remove the divider's power draw and its \\( N^{2} \\) noise contribution; a digital-to-time converter with roughly 100 fs resolution cancels the fractional residue, though DTC noise is multiplied by \\( N^{2} \\) and nonlinearity causes noise folding and fractional spurs.[17](https://www.mdpi.com/2072-666X/16/3/333) • [18](https://www.benjamin.hershberg.com/wp-content/papercite-data/papers/2016-jssc-fnsspll-2pmod.pdf)\n\n**Hybrid architectures.** A DDS inserted in the reference or feedback path gives fine resolution without lowering the phase-detector frequency, though DDS spurs are degraded by the loop division ratio.[19](https://www.highfrequencyelectronics.com/Aug08/HFE0808_Chenakin4.pdf) [Frequency](https://www.edgepedia.org/frequency) mixing in the feedback path similarly minimizes the division ratio, and inserting a multiplier instead of a divider suppresses residual phase noise at the 20·log(N) rate.[20](https://dl.cdn-anritsu.com/en-en/about-anritsu/r-d/technical/e-31/31-06.pdf)\n\n## Applications\n\nThe delta-sigma fractional-N technique was developed with monolithic 1–2 GHz mobile-radio synthesizers in short-channel BiCMOS in mind.[16](https://ewh.ieee.org/r5/denver/sscs/References/1993_05_Riley.pdf) DDS is generally preferred at low frequencies up to several MHz and for high-speed switching such as high-performance radar.[2](https://www.am1.us/wp-content/uploads/2017/11/Advanced-Phase-Lock-Applications-Synthesis-Ch5-V1.1.pdf) [Microwave](https://www.edgepedia.org/microwave) signal generators combine references: Anritsu achieved −140 dBc/Hz phase noise at 10 GHz output and 10 kHz offset using a combined 10 MHz OCXO, 100 MHz OCXO, and 1.6 GHz DRO reference with multiplier-in-loop synthesis.[20](https://dl.cdn-anritsu.com/en-en/about-anritsu/r-d/technical/e-31/31-06.pdf) Since 2023 the integrated-synthesizer frontier has moved to sub-100-femtosecond jitter, and a 2026 fractional-N charge-pump PLL in 0.18 µm SiGe BiCMOS covers 6–24 GHz continuously with 77.6 fs rms jitter and a gain-enhanced PFD that cuts in-band noise by 26 dB versus a conventional PFD.[21](https://onlinelibrary.wiley.com/doi/full/10.1002/mop.70521)\n\n## Limitations and alternatives\n\nThree noise sources dominate a PLL output: crystal phase noise close to the carrier (below roughly 10–100 Hz), phase-detector noise from about 10–50 Hz up to the loop bandwidth, and VCO noise beyond it.[3](https://www.ti.com/lit/an/swra029/swra029.pdf) In-band flat noise follows \\( \\mathrm{PN}_{\\mathrm{flat}}(f) \\), so reducing N by ten at constant output improves flat noise by 10 dB. Reference spurs are also multiplied by N at unchanged offset: a −100 dBc spur on a 1 MHz reference becomes −40 dBc at a 1 GHz output with N = 1000.[3](https://www.ti.com/lit/an/swra029/swra029.pdf) Fractional spurs fall into integer-boundary, primary fractional, and sub-fractional classes, and good fractional-N ASICs compensate to −40 dBc or better.[3](https://www.ti.com/lit/an/swra029/swra029.pdf) Realized fractional-N gains fall short of theory because the fractional circuitry adds noise and spurs of its own. Fractional-N designs remain prone to higher in-band noise and spurs than integer-N counterparts, driving mitigation techniques such as successive requantizers, probability mass redistribution, and DTC nonlinearity cancellation.[22](https://link.springer.com/chapter/10.1007/978-3-030-91741-8_13)\n\nDDS failure modes differ: higher-order harmonics fold back into the Nyquist bandwidth and cannot be filtered out, the sin(x)/x response is down 3.92 dB at Nyquist, and the DAC sets spurious performance and dominates power.[4](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf) • [2](https://www.am1.us/wp-content/uploads/2017/11/Advanced-Phase-Lock-Applications-Synthesis-Ch5-V1.1.pdf) Against a free-running VCO, a locked synthesizer suppresses the VCO's low close-in noise within the PLL loop bandwidth, with the output noise dominated by reference and other in-band PLL noise; against multiplier chains, a multiplier-in-loop PLL suppresses rather than degrades residual noise.[20](https://dl.cdn-anritsu.com/en-en/about-anritsu/r-d/technical/e-31/31-06.pdf) • [24](https://www.analog.com/en/resources/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-2.html)\n\n## References\n\n1. [Microwave Frequency Synthesizers: A Tutorial (Alexander Chenakin, IEEE Microwave Magazine, 2023)](https://doi.org/10.1109/mmm.2023.3265464)\n2. [Advanced Phase-Lock Applications: Frequency Synthesis, Chapter 5 (James A. Crawford)](https://www.am1.us/wp-content/uploads/2017/11/Advanced-Phase-Lock-Applications-Synthesis-Ch5-V1.1.pdf)\n3. [Fractional/Integer-N PLL Basics (Texas Instruments)](https://www.ti.com/lit/an/swra029/swra029.pdf)\n4. [MT-085: Fundamentals of Direct Digital Synthesis (DDS) (Analog Devices)](https://www.analog.com/media/en/training-seminars/tutorials/mt-085.pdf)\n5. [ADF41513 (Rev.A) datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/adf41513.pdf)\n6. [A 14GHz Chopper-Refolding Sampling PLL Achieving 33.8 fs_rms and −80.8dBc Reference Spur with a kT/C-Noise-Cancellation SPD (ISSCC 2026)](https://doi.org/10.1109/isscc49663.2026.11409284)\n7. [Phase Locked Loop Circuits (UCSB ECE145B course notes)](https://web.ece.ucsb.edu/~long/ece145b/PLL_intro_FMD_FS.pdf)\n8. [H.J. Finden (1943). The frequency synthesizer. The journal of the Institution of Electrical Engineers. Part 3, Communication engineering.](https://doi.org/10.1049/ji-3-1.1943.0031)\n9. [Gaston Salmet (1956). An Analysis of Pulse-Synchronized Oscillators. Proceedings of the IRE.](https://doi.org/10.1109/jrproc.1956.274877)\n10. [B. M. Wojciechowski (1960). Theory of a Frequency-Synthesizing Network. Bell System Technical Journal.](https://doi.org/10.1002/j.1538-7305.1960.tb03937.x)\n11. [G. Husson, B.N. Sherman (1961). A transistorized frequency synthesizer. Journal of the British Institution of Radio Engineers.](https://doi.org/10.1049/jbire.1961.0044)\n12. [Frequency Synthesizers, A Survey of Techniques (J. Noordanus, IRE Transactions on Communications Systems, 1969)](https://doi.org/10.1109/tcom.1969.1090079)\n13. [US Patent 4,145,667: Phase locked loop frequency synthesizer using digital modulo arithmetic (Bell Telephone Laboratories)](https://www.freepatentsonline.com/4145667.html)\n14. [Venceslav F. Kroupa (1998). Direct Digital Frequency Synthesizers. .](https://doi.org/10.1109/9780470544396)\n15. [Integrated Circuit Design for High-Speed Frequency Synthesis (book preview)](https://api.pageplace.de/preview/DT0400.9781580539838_A25416332/preview-9781580539838_A25416332.pdf)\n16. [Delta-sigma modulation in fractional-N frequency synthesis (Riley, Copeland, Kwaśniewski, IEEE JSSC 1993)](https://ewh.ieee.org/r5/denver/sscs/References/1993_05_Riley.pdf)\n17. [A Review on Micro-Watts All-Digital Frequency Synthesizers (Micromachines, 2025)](https://www.mdpi.com/2072-666X/16/3/333)\n18. [A DTC-based fractional-N sub-sampling PLL for phase modulation (JSSC 2016, Hershberg et al.)](https://www.benjamin.hershberg.com/wp-content/papercite-data/papers/2016-jssc-fnsspll-2pmod.pdf)\n19. [Building a Microwave Synthesizer (Chenakin, High Frequency Electronics)](https://www.highfrequencyelectronics.com/Aug08/HFE0808_Chenakin4.pdf)\n20. [ANRITSU TECHNICAL REVIEW No.31: Phase Noise Suppression in PLL Synthesizers](https://dl.cdn-anritsu.com/en-en/about-anritsu/r-d/technical/e-31/31-06.pdf)\n21. [Ultra Low Jitter Wideband Frequency Synthesizer With Gain-Enhanced PFD (Wu et al., 2026, Microwave and Optical Technology Letters)](https://onlinelibrary.wiley.com/doi/full/10.1002/mop.70521)\n22. [Recent Advances in Fractional-N Frequency Synthesis (Springer chapter)](https://link.springer.com/chapter/10.1007/978-3-030-91741-8_13)\n23. [Snap003 (ti.com)](https://www.ti.com/lit/pdf/snap003)\n24. [Pll for High Frequency Receivers and Transmitters 2, analog.com](https://www.analog.com/en/resources/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-2.html)\n\n---\n*Topic: Encyclopedia › Technology and the built world › Engineering and manufacturing › Electrical and electronics engineering › Circuits and signal processing*\n\n*Initially written Sep 29, 2026 · Reviewed: Sep 30, 2026 · Edited: Sep 30, 2026; Oct 21, 2026 · Last review: Sep 30, 2026*\n\n*Copyright 2026 EdgeChat AI, a subsidiary of Biostate AI.*\n\nLicense: Edgepedia Community License 1.0, https://www.edgepedia.org/edgepedia/license\n",
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