{ "id": "ep7cn5e4jk", "slug": "lockstep-computing", "title": "Lockstep (computing)", "updated": "2026-10-15", "topic_path": [ { "id": "technology", "label": "Technology and the built world", "api_url": "https://www.edgepedia.org/api/v1/topics/technology" }, { "id": "technology.computing", "label": "Computing and digital systems", "api_url": "https://www.edgepedia.org/api/v1/topics/technology.computing" }, { "id": "technology.computing.ai", "label": "Artificial intelligence and data", "api_url": "https://www.edgepedia.org/api/v1/topics/technology.computing.ai" }, { "id": "technology.computing.ai.algorithms", "label": "Algorithms and computational methods", "api_url": "https://www.edgepedia.org/api/v1/topics/technology.computing.ai.algorithms" } ], "geo": [ { "id": "geo.nongeo.t1946.technology.computing.ai.algorithms", "label": "Non-geographic · 1946 to 2000: Algorithms and computational methods", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology.computing.ai.algorithms", "path": [ { "id": "geo.nongeo", "label": "Non-geographic", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo" }, { "id": "geo.nongeo.t1946", "label": "Non-geographic · 1946 to 2000", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946" }, { "id": "geo.nongeo.t1946.technology", "label": "Technology and the built world", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology" }, { "id": "geo.nongeo.t1946.technology.computing", "label": "Computing and digital systems", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology.computing" }, { "id": "geo.nongeo.t1946.technology.computing.ai", "label": "Artificial intelligence and data", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology.computing.ai" }, { "id": "geo.nongeo.t1946.technology.computing.ai.algorithms", "label": "Algorithms and computational methods", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology.computing.ai.algorithms" } ] } ], "excerpt": "Lockstep is a synchronization method in which processors or simulation components advance together in coordinated steps: in hardware, two processors execute the same instructions from the same clock, one checking for errors.", "snippet": "Lockstep is a synchronization method in which processors or simulation components advance together in coordinated steps: in hardware, two processors execute the same instructions from the same clock, one checking for errors.", "node": "technology.computing.ai.algorithms", "markdown": "# Lockstep (computing)\n\nLockstep is a synchronization method in which processors or simulation components advance together in coordinated steps rather than independently. The term covers two distinct practices. In hardware, a lockstep system is one in which two processors execute the same instructions simultaneously, based on the same clock, with one updating memory and I/O while the other checks for mismatches.[1](https://docs.amd.com/api/khub/documents/2ltSPVPc3fSsubW6xw9ecA/content) In parallel discrete-event simulation, lockstep means that simulation components advance through a global time step or barrier: each round computes which events are safe to process, processes them, exchanges messages, and synchronizes before the next round.[2](https://www.net.in.tum.de/pub/simulationstechnik/ws20112012/skript/ST_WS20112012_Ch6_ParallelSim.pdf) What is synchronized differs accordingly: instructions and clock cycles in hardware, simulation time steps in simulation.\n\n| Key fact | Value |\n|---|---|\n| Hardware lockstep definition | Two processors execute the same instructions simultaneously from the same clock[1](https://docs.amd.com/api/khub/documents/2ltSPVPc3fSsubW6xw9ecA/content) |\n| DCLS resource cost | Double the processor resources, in exchange for almost immediate error detection[3](https://www.mdpi.com/2079-9292/12/2/464) |\n| Simulation lockstep bound | \\( \\mathrm{LBTS} = \\min(N_{i} + \\mathrm{LA}_{i}) \\), each process's next event time plus its lookahead; events with timestamp \\( \\le \\mathrm{LBTS} \\) are safe[2](https://www.net.in.tum.de/pub/simulationstechnik/ws20112012/skript/ST_WS20112012_Ch6_ParallelSim.pdf) |\n| GPU warp size | Subgroups (warps in CUDA) typically contain 16–128 threads depending on architecture[4](https://arbersephirotheca.github.io/files/PLDI-simt-step.pdf) |\n| VDCLS performance cost | Dhrystone 1.24 vs 1.38 DMIPS/Hz; about 4% additional FPGA resource use[3](https://www.mdpi.com/2079-9292/12/2/464) |\n| FMI co-simulation step | Time advances in steps negotiated via fmi3DoStep with currentCommunicationPoint and communicationStepSize[5](https://fmi-standard.org/docs/3.0.2/) |\n\n## How it works\n\nIn parallel discrete-event simulation, each logical process (LP) holds a local clock and a queue of timestamped events. The goal of synchronization is to ensure each LP processes events in timestamp order; if every LP does so, no causality error can occur, a condition called the local causality constraint.[2](https://www.net.in.tum.de/pub/simulationstechnik/ws20112012/skript/ST_WS20112012_Ch6_ParallelSim.pdf) • [6](https://api.drum.lib.umd.edu/server/api/core/bitstreams/29292ec1-2127-4185-b310-3da953b26a67/content) Conservative lockstep schemes satisfy the constraint by waiting: the principal task of any conservative protocol is to determine when it is \"safe\" to process an event, meaning no event with a smaller timestamp can still arrive.[7](https://www.cs.auckland.ac.nz/courses/compsci703s1c/archive/2008/resources/mano/Fujimoto-Simulation.pdf)\n\nSafety is established with a lower bound on future arrivals. Each round computes the Lower Bound on the Time Stamp, \\( \\mathrm{LBTS} = \\min(N_{i} + \\mathrm{LA}_{i}) \\), where \\( N_{i} \\) is process i's next event time and \\( \\mathrm{LA}_{i} \\) is its lookahead, the amount by which a process can predict its future message times.[2](https://www.net.in.tum.de/pub/simulationstechnik/ws20112012/skript/ST_WS20112012_Ch6_ParallelSim.pdf) Events with timestamp at or below LBTS are safe. Optimistic schemes instead allow violations and recover: Time Warp, introduced by David R. Jefferson in 1985, detects out-of-order execution and rolls it back using saved state and anti-messages that annihilate their matching positive messages.[8](https://doi.org/10.1145/3916.3988) • [7](https://www.cs.auckland.ac.nz/courses/compsci703s1c/archive/2008/resources/mano/Fujimoto-Simulation.pdf) Conservative and optimistic synchronization remain the two major classes of parallel discrete-event simulation algorithms.[9](https://www.cs.cmu.edu/~bryant/pubdir/wsc17.pdf)\n\nIn hardware, the mechanism is duplication rather than barriers. Two identical cores execute the same instruction flow with a time stagger, so their internal electrical state differs at any point in time.[10](https://export.arxiv.org/pdf/2307.15436v1.pdf)\n\n## How it is done\n\nThe conservative simulation loop cycles through these steps[2](https://www.net.in.tum.de/pub/simulationstechnik/ws20112012/skript/ST_WS20112012_Ch6_ParallelSim.pdf):\n\n1. Compute the LBTS each LP might later receive.\n2. Process the events with timestamp \\( \\le \\mathrm{LBTS} \\), which are safe.\n3. Exchange messages (or null messages, which promise not to send a smaller-timestamp message later; the null-message algorithm avoids deadlock provided timestamp increments are non-zero).[11](https://cs.rpi.edu/~chrisc/rc-web/node4.html)\n4. Barrier-synchronize and repeat.\n\nConservative Time Windows variants iterate by lock-stepping over two barrier-synchronized phases, window identification and event processing.[6](https://api.drum.lib.umd.edu/server/api/core/bitstreams/29292ec1-2127-4185-b310-3da953b26a67/content)\n\nHardware lockstep runs two identical processors on the same clock with a temporal delay between them. Microchip's RT PolarFire uses a delay of 0.5 to 2 clock cycles, which the vendor states is appropriate to detect most common errors, with a comparator flagging differences cycle by cycle.[12](https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ApplicationNotes/ApplicationNotes/Microchip_RT_PolarFire_FPGA_Lockstep_Processor_AN4228.pdf) The delay need not be constant: in a sample VDCLS execution trace the slave core stayed three to seven clock cycles behind the master.[3](https://www.mdpi.com/2079-9292/12/2/464) In co-simulation under the Functional Mock-up Interface (FMI), the importer's algorithm calls fmi3DoStep with a currentCommunicationPoint and a communicationStepSize, so all simulation units advance through negotiated communication points in lockstep.[5](https://fmi-standard.org/docs/3.0.2/) • [13](https://clagms.github.io/assets/pdfs/Hansen2022.pdf)\n\n## Origin\n\nConservative synchronization addresses the synchronization problem and its first algorithms.[9](https://www.cs.cmu.edu/~bryant/pubdir/wsc17.pdf) • [7](https://www.cs.auckland.ac.nz/courses/compsci703s1c/archive/2008/resources/mano/Fujimoto-Simulation.pdf) Chandy and Misra's 1981 Communications of the ACM paper reported a scheme in which the multiprocessor network is allowed to deadlock, the deadlock is detected in a distributed manner using a modification of the Dijkstra-Scholten termination detection scheme, and then the deadlock is broken; the scheme needs bounded memory, no more than sequential simulation, and no global clock, since every process maintains its own local clock.[14](https://doi.org/10.1145/358598.358613) Time Warp founded optimistic synchronization[9](https://www.cs.cmu.edu/~bryant/pubdir/wsc17.pdf), with Jefferson's \"Virtual time\" published in ACM TOPLAS in 1985.[8](https://doi.org/10.1145/3916.3988) Later windowing work includes David M. Nicol's YAWNS global-window approach[15](https://doi.org/10.1145/151261.151266), Jeff S. Steinman's Breathing Time Warp[16](https://doi.org/10.1145/174134.158473), and composite synchronization by Nicol and Liu.[17](https://doi.org/10.1109/tpds.2002.1003854)\n\n## Variants\n\n**Dual-core lockstep (DCLS)** couples two cores so only one is visible at user level while both execute the same instruction flow with time staggering; it is generally implemented at hardware level.[10](https://export.arxiv.org/pdf/2307.15436v1.pdf) **Triple-core lockstep (TCLS)** adds a third core with majority voting, enabling immediate state restoration but with large resource overhead.[3](https://www.mdpi.com/2079-9292/12/2/464) **Variable delayed DCLS (VDCLS)** lets the inter-core delay vary, reducing [Dhrystone](https://www.edgepedia.org/dhrystone) performance from 1.38 to 1.24 DMIPS/Hz and CoreMark from 2.10 to 2.04 CoreMark/MHz at about 4% additional FPGA resource use.[3](https://www.mdpi.com/2079-9292/12/2/464) **Software-based lockstep** with a hardware observer on a dual-core ARM improved benchmark cross section by one order of magnitude under proton irradiation and fault injection, even in the worst case.[18](https://ieeexplore.ieee.org/document/9706422) **FlexStep** duplicates user threads on any core through a configurable interconnect supporting one-to-one (DCLS-like) or one-to-two (TCLS-like) verification, rather than statically binding identical cores.[19](http://www.arxiv.org/pdf/2503.13848)\n\nOn GPUs, earlier specifications modeled lockstep subgroup execution, with all converged threads advancing together instruction by instruction; lockstep remains a common developer mental model, but specifications have shifted away from it.[4](https://arbersephirotheca.github.io/files/PLDI-simt-step.pdf) In FMI co-simulation, the orchestrator finds communication points that minimize co-simulation error while ensuring all simulation units move in lockstep.[13](https://clagms.github.io/assets/pdfs/Hansen2022.pdf)\n\n## Applications\n\nHardware lockstep is used in safety-critical and security hardware.[20](https://www.chipsalliance.org/news/implementing-dual-core-lockstep-in-the-veer-el2-risc-v-core/) A lockstep dual-core [ARM Cortex-A9](https://www.edgepedia.org/arm-cortex-a9) in a [Xilinx Zynq](https://www.edgepedia.org/xilinx-zynq)-7000 mitigated around 91% of soft errors in experiments[21](https://link.springer.com/chapter/10.1007/978-3-319-56258-2_17), and CHIPS Alliance applies DCLS in the open-source VeeR EL2 RISC-V core, where it also protects Root of Trust macros such as Caliptra against side-channel attacks and error injection when an attacker gains physical access to the chip.[20](https://www.chipsalliance.org/news/implementing-dual-core-lockstep-in-the-veer-el2-risc-v-core/) FMI co-simulation, supported by more than 200 tools, uses negotiated communication points as its lockstep mechanism.[5](https://fmi-standard.org/docs/3.0.2/)\n\n## Limitations and alternatives\n\n**Costs in hardware.** DCLS doubles processor resources.[3](https://www.mdpi.com/2079-9292/12/2/464) Quantified overheads of flexible schemes are smaller: FlexStep reports a 1.07% slowdown, 2.21% area overhead, and 2.89% power consumption with microsecond-level detection latency on an AMD Alveo U280 FPGA.[19](http://www.arxiv.org/pdf/2503.13848)\n\n**Costs in simulation.** Conservative protocols are greatly limited by lookahead, and a classical result states that the speed of conservative simulations is limited by the length of the critical chain of events.[22](https://www.eurosis.org/conf/isc/isc2003/tutorial.pdf) Zero-lookahead cycles are not allowed, and conservative systems cannot fully exploit available parallelism because they must protect against a worst case; optimistic systems instead pay state-saving overhead that may severely degrade performance, and rollback thrashing can occur.[2](https://www.net.in.tum.de/pub/simulationstechnik/ws20112012/skript/ST_WS20112012_Ch6_ParallelSim.pdf) On the theoretical balance, Lipton and Mizell showed Time Warp can outperform the Chandy/Misra algorithms by an arbitrary factor, while the Null Message algorithm can only outperform Time Warp by a constant factor.[11](https://cs.rpi.edu/~chrisc/rc-web/node4.html)\n\n**Failure modes.** Deadlock is the classical conservative failure: the Chandy-Misra 1981 scheme deliberately allows deadlock, detects it, and breaks it.[14](https://doi.org/10.1145/358598.358613) In FMI co-simulation, semantic violations by simulation units lead to deadlock in the UPPAAL verification model[13](https://clagms.github.io/assets/pdfs/Hansen2022.pdf), and deterministic lockstep co-simulation requires FMUs to be memoryless or implement rollback (fmiGetFMUstate/fmiSetFMUstate) or step-size prediction, with at most one \"legacy\" FMU lacking these capabilities.[23](https://apps.dtic.mil/sti/pdfs/ADA587399.pdf) Non-determinism is a further hazard: because FMI functions may not be thread-safe, mutual exclusion must be handled properly, since race conditions would break co-simulation repeatability.[24](https://ogst.ifpenergiesnouvelles.fr/articles/ogst/full_html/2019/01/ogst180065/ogst180065.html)\n\n**Bridging the two regimes.** Conservative simulators require lookahead but not rollback; optimistic simulators require rollback but not lookahead, and the two have often been treated as incompatible. Unified virtual time (UVT) executes events conservatively when lookahead is available (\\( \\mathrm{GVT} \\le \\mathrm{LVT} < \\mathrm{CVT} \\)) and optimistically otherwise (\\( \\mathrm{CVT} \\le \\mathrm{LVT} \\)), treating conservative execution as an accelerator on top of a basically optimistic engine.[25](https://www.informs-sim.org/wsc17papers/includes/files/058.pdf)\n\n## References\n\n1. [AMD/Xilinx documentation on processor lockstep](https://docs.amd.com/api/khub/documents/2ltSPVPc3fSsubW6xw9ecA/content)\n2. [Parallele Simulation (lecture notes, Chapter 6: Parallel Simulation, TU München)](https://www.net.in.tum.de/pub/simulationstechnik/ws20112012/skript/ST_WS20112012_Ch6_ParallelSim.pdf)\n3. [Variable Delayed Dual-Core Lockstep (VDCLS) Processor for Safety and Security Applications](https://www.mdpi.com/2079-9292/12/2/464)\n4. [SIMT-Step Execution: A Flexible Operational Semantics for GPU Subgroup Behavior (PLDI)](https://arbersephirotheca.github.io/files/PLDI-simt-step.pdf)\n5. [Functional Mock-up Interface Specification 3.0.2](https://fmi-standard.org/docs/3.0.2/)\n6. [Parallel and distributed simulation of discrete event systems (survey, University of Maryland repository)](https://api.drum.lib.umd.edu/server/api/core/bitstreams/29292ec1-2127-4185-b310-3da953b26a67/content)\n7. [Parallel and Distributed Simulation Systems (Fujimoto, tutorial/Winter Simulation Conference paper)](https://www.cs.auckland.ac.nz/courses/compsci703s1c/archive/2008/resources/mano/Fujimoto-Simulation.pdf)\n8. [David R. Jefferson (1985). Virtual time. ACM Transactions on Programming Languages and Systems.](https://doi.org/10.1145/3916.3988)\n9. [Perspectives on the Origin and Evolution of Parallel Discrete Event Simulation (Winter Simulation Conference 2017)](https://www.cs.cmu.edu/~bryant/pubdir/wsc17.pdf)\n10. [SafEDE (arXiv 2307.15436, 2023; also circulated as a university-repository copy)](https://export.arxiv.org/pdf/2307.15436v1.pdf)\n11. [Parallel Simulation Technologies (Carothers, RPI course notes)](https://cs.rpi.edu/~chrisc/rc-web/node4.html)\n12. [RT PolarFire Lockstep Processor Application Note (AN4228, Microchip)](https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ApplicationNotes/ApplicationNotes/Microchip_RT_PolarFire_FPGA_Lockstep_Processor_AN4228.pdf)\n13. [Verification and synthesis of co-simulation algorithms subject to algebraic loops and adaptive steps (Hansen 2022, author-hosted copy)](https://clagms.github.io/assets/pdfs/Hansen2022.pdf)\n14. [K. M. Chandy, J. Misra (1981). Asynchronous distributed simulation via a sequence of parallel computations. Communications of the ACM.](https://doi.org/10.1145/358598.358613)\n15. [David M. Nicol (1993). The cost of conservative synchronization in parallel discrete event simulations. Journal of the ACM.](https://doi.org/10.1145/151261.151266)\n16. [Jeff S. Steinman (1993). Breathing Time Warp. ACM SIGSIM Simulation Digest.](https://doi.org/10.1145/174134.158473)\n17. [D.M. Nicol, J. Liu (2002). Composite synchronization in parallel discrete-event simulation. IEEE Transactions on Parallel and Distributed Systems.](https://doi.org/10.1109/tpds.2002.1003854)\n18. [Dual-core lockstep hybrid approach with software-based lockstep and hardware observer on ARM](https://ieeexplore.ieee.org/document/9706422)\n19. [FlexStep (arXiv preprint, 2025)](http://www.arxiv.org/pdf/2503.13848)\n20. [Dual-core Lockstep in the VeeR EL2 RISC-V core for safety-critical applications and side-channel access mitigation in Caliptra RoT | CHIPS Alliance](https://www.chipsalliance.org/news/implementing-dual-core-lockstep-in-the-veer-el2-risc-v-core/)\n21. [Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC](https://link.springer.com/chapter/10.1007/978-3-319-56258-2_17)\n22. [Tutorial: Lookahead, Rollback and Lookback, Quest for Parallelism in Discrete Event Simulation (Szymanski & Chen, ISC 2003)](https://www.eurosis.org/conf/isc/isc2003/tutorial.pdf)\n23. [Determinate composition of FMUs for co-simulation (Broman et al., EMSOFT 2013; DTIC copy)](https://apps.dtic.mil/sti/pdfs/ADA587399.pdf)\n24. [A method for parallel scheduling of multi-rate co-simulation on multi-core platforms (Oil & Gas Science and Technology, 2019)](https://ogst.ifpenergiesnouvelles.fr/articles/ogst/full_html/2019/01/ogst180065/ogst180065.html)\n25. [Virtual Time III: Unification of Conservative and Optimistic Synchronization in Parallel Discrete Event Simulation (Winter Simulation Conference 2017)](https://www.informs-sim.org/wsc17papers/includes/files/058.pdf)\n\n---\n*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Artificial intelligence and data › Algorithms and computational methods*\n\n*Initially written Sep 29, 2026 · Edited: Oct 15, 2026*\n\n*Copyright 2026 EdgeChat AI, a subsidiary of Biostate AI.*\n\nLicense: Edgepedia Community License 1.0, https://www.edgepedia.org/edgepedia/license\n", "same_as": [ "https://www.cs.cmu.edu/~bryant/pubdir/wsc17.pdf", "https://cs.rpi.edu/~chrisc/rc-web/node4.html" ], "url": "https://www.edgepedia.org/lockstep-computing", "markdown_url": "https://www.edgepedia.org/lockstep-computing.md", "license": { "name": "Edgepedia Community License 1.0", "url": "https://www.edgepedia.org/edgepedia/license", "summary": "Free with credit, commercial use included. AI training is open to everyone. For other uses, organizations over USD 100M in revenue or 100M monthly users license separately.", "spdx": "LicenseRef-Edgepedia-Community-1.0" }, "credit": "\"Lockstep (computing)\", Edgepedia (EdgeChat), https://www.edgepedia.org/lockstep-computing. Edgepedia Community License 1.0.", "credit_md": "\"[Lockstep (computing)](https://www.edgepedia.org/lockstep-computing)\", Edgepedia (EdgeChat), [https://www.edgepedia.org/lockstep-computing](https://www.edgepedia.org/lockstep-computing). [Edgepedia Community License 1.0](https://www.edgepedia.org/edgepedia/license).", "credit_html": "\"Lockstep (computing)\", Edgepedia (EdgeChat), https://www.edgepedia.org/lockstep-computing. Edgepedia Community License 1.0.", "speakable": "Lockstep is a synchronization method in which processors or simulation components advance together in coordinated steps: in hardware, two processors execute the same instructions from the same clock, one checking for errors." }