{ "id": "epkcb8jggs", "slug": "strain-engineering", "title": "Strain engineering", "updated": "2026-09-30", "topic_path": [ { "id": "technology", "label": "Technology and the built world", "api_url": "https://www.edgepedia.org/api/v1/topics/technology" }, { "id": "technology.engineering", "label": "Engineering and manufacturing", "api_url": "https://www.edgepedia.org/api/v1/topics/technology.engineering" }, { "id": "technology.engineering.engineering.materials.metallurgy", "label": "Materials science and metallurgy", "api_url": "https://www.edgepedia.org/api/v1/topics/technology.engineering.engineering.materials.metallurgy" } ], "geo": [ { "id": "geo.nongeo.t1946.technology.engineering.engineering.materials.metallurgy", "label": "Non-geographic · 1946 to 2000: Materials science and metallurgy", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology.engineering.engineering.materials.metallurgy", "path": [ { "id": "geo.nongeo", "label": "Non-geographic", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo" }, { "id": "geo.nongeo.t1946", "label": "Non-geographic · 1946 to 2000", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946" }, { "id": "geo.nongeo.t1946.technology", "label": "Technology and the built world", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology" }, { "id": "geo.nongeo.t1946.technology.engineering", "label": "Engineering and manufacturing", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology.engineering" }, { "id": "geo.nongeo.t1946.technology.engineering.engineering.materials.metallurgy", "label": "Materials science and metallurgy", "api_url": "https://www.edgepedia.org/api/v1/geo/geo.nongeo.t1946.technology.engineering.engineering.materials.metallurgy" } ] } ], "excerpt": "Strain engineering deliberately applies elastic strain to crystals or thin films to change their properties; strained silicon became standard in 90, 65, and 45 nm CMOS logic.", "snippet": "Strain engineering deliberately applies elastic strain to crystals or thin films to change their properties; strained silicon became standard in 90, 65, and 45 nm CMOS logic.", "node": "technology.engineering.engineering.materials.metallurgy", "markdown": "# Strain engineering\n\nStrain engineering is the deliberate application of elastic mechanical strain to a crystal or thin film in order to change its electronic, optical, thermal, or structural properties. [Strained silicon](https://www.edgepedia.org/strained-silicon) channels were adopted as a performance boost at the 90 nm logic node, amid increasingly difficult scaling, and became a standard performance feature of 90, 65, and 45 nm technologies,[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8) and the same principle now extends from bulk crystals to atomically thin semiconductors, where strain can tune mobility, band gap, phonons, and even thermal conductivity by large factors.[2](http://li.mit.edu/Archive/Papers/24/Shi24TsymbalovPNAS.pdf) • [3](https://europepmc.org/article/med/35950446)\n\n| Key fact | Value |\n|---|---|\n| Industrial deployment | Intel's 90 nm logic used strained Si, raising n- and p-type drive currents by 10% and 25%[4](https://web.stanford.edu/class/ee311/NOTES/Intel%20Strain%20Si%20EDL04.pdf) |\n| Mobility gain in Si | nMOSFET mobility rises up to 15% per 1% tensile strain; up to 40% in thin-film transistors at about 0.6% strain[5](https://iopscience.iop.org/article/10.1088/1361-648X/ad649f) |\n| Mobility gain in MoS2 | Electron mobility in monolayer MoS2 transistors enhances at 130 ± 40% per % strain[6](https://pubs.acs.org/ancac3/article/18/19/12377/150464/Enhancing-Carrier-Mobility-in-Monolayer-MoS2) |\n| Band-gap gauge factors | WS2 shifts at about 59 meV/% uniaxial versus about 135 meV/% biaxial; MoS2 rates of 43 to 73 meV/% are calculated, with one experiment reporting 400 meV/%[7](https://pubs.acs.org/nalefd/article/24/41/12722/149668/Bandgap-Engineering-of-2D-Materials-toward-High) • [8](https://link.aps.org/accepted/10.1103/PhysRevB.110.144109) |\n| Strain limits | Bulk silicon breaks at strains of 1.5% or less; graphene sustains elastic strains up to 25%[9](https://www.nature.com/articles/s41377-020-00421-5) |\n| Thermal conductivity | Elastic strain can raise diamond's room-temperature lattice thermal conductivity by more than 100% or cut it by more than 95%, spanning sub-100 to 6,000 W·m⁻¹·K⁻¹[2](http://li.mit.edu/Archive/Papers/24/Shi24TsymbalovPNAS.pdf) |\n\n## How it works\n\nStrain changes electronic structure through deformation potentials, the energy shifts of band edges per unit strain, a framework laid out by J. Bardeen and W. Shockley in \"Deformation Potentials and Mobilities in Non-Polar Crystals\" ([Physical Review](https://www.edgepedia.org/physical-review), 1950).[10](https://doi.org/10.1103/physrev.80.72) Under this theory a biaxial strain splits band-edge shifts into a hydrostatic part, which preserves the unit cell's symmetry, and a shear part, which preserves its volume.[5](https://iopscience.iop.org/article/10.1088/1361-648X/ad649f) A strain Hamiltonian built on symmetry grounds is formally identical to the \\( k \\cdot p \\) Hamiltonian under the correspondence \\( k_i \\cdot k_j \\leftrightarrow \\epsilon_{ij} \\), with the total Hamiltonian written \\( H = H_{kp} + H_{\\mathrm{strain}} \\); cubic crystals need at most three independent deformation potentials at a given \\( k \\) point.[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8)\n\nThe practical consequence in silicon is band splitting, warping, and carrier repopulation: degenerate valleys or valence bands separate, carriers repopulate into states with lower conductivity effective mass and altered scattering rates, and mobility rises.[11](https://www.annualreviews.org/content/journals/10.1146/annurev-matsci-082908-145312) In strained Si the effective-mass contribution alone caps electron mobility enhancement at \\( 3m_l/(2m_l+m_t) = 1.36 \\) when only two valleys are occupied.[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8) Direction matters: density functional theory shows TMD band gaps shrink under tensile and grow under compressive strain, while black phosphorus behaves oppositely because of the bonding character of its band edges.[12](https://pubs.aip.org/aip/jap/article/136/9/090901/3311660/Strain-engineering-in-2D-FETs-Physics-status-and)\n\n## How it is done\n\nIn silicon CMOS, strain is process-induced: selective epitaxial SiGe in source/drain regions compresses pMOS channels longitudinally, and a tensile silicon nitride capping layer stretches nMOS channels.[4](https://web.stanford.edu/class/ee311/NOTES/Intel%20Strain%20Si%20EDL04.pdf) For 2D materials the main routes are bending a flexible substrate with pins, growth at about 1000 °C on a substrate with a different thermal expansion coefficient, and deposited capping or stressor layers; wafer bending reaches about 2.2% tensile but only −0.2% compressive strain, while capping layers reach 0.85% in both signs and allow per-transistor strain.[12](https://pubs.aip.org/aip/jap/article/136/9/090901/3311660/Strain-engineering-in-2D-FETs-Physics-status-and) Iterative MgO\\(_x\\) stressor deposition gives uniform tensile strain up to 0.48 ± 0.05% in monolayer MoS2 at 150 nm thickness.[6](https://pubs.acs.org/ancac3/article/18/19/12377/150464/Enhancing-Carrier-Mobility-in-Monolayer-MoS2) Other routes include polymer encapsulation on flexible substrates, which transferred 4.3% uniaxial strain to few-layer 3R-MoS2,[13](https://pubs.aip.org/aip/apl/article/128/25/251107/3396330/Efficient-and-anisotropic-strain-engineering-in) and focused-ion-beam implantation, which produced record tensile strains in single-crystal Si membranes of 3.1% biaxial and 8.5% uniaxial.[5](https://iopscience.iop.org/article/10.1088/1361-648X/ad649f)\n\nStrain is characterized mainly optically. Raman peak shifts are converted to strain through Grüneisen parameters (for biaxial strain in MoS2, \\( \\gamma_{E^1_{2g}} = 0.68 \\) and \\( \\gamma_{A_{1g}} = 0.21 \\)), solved jointly with doping in a linear system.[6](https://pubs.acs.org/ancac3/article/18/19/12377/150464/Enhancing-Carrier-Mobility-in-Monolayer-MoS2) [Photoluminescence](https://www.edgepedia.org/photoluminescence) shifts give the band-gap change directly; the E′ Raman mode of MoS2 redshifts at about 7.4 cm⁻¹/% strain.[14](https://www.nature.com/articles/s41467-020-15023-3) Nonuniform strain fields can be mapped by moiré-pattern magnification and second-harmonic generation.[15](https://google.iopscience.iop.org/article/10.1088/1361-6633/ad06db)\n\n## Origin\n\nThe physics descends from deformation potential theory, laid out by J. Bardeen and W. Shockley in Physical Review in 1950,[10](https://doi.org/10.1103/physrev.80.72) and from piezoresistance measurements in Si and Ge that date to the mid-1950s; deformation potentials were applied to transport in strained semiconductors soon after, attributing mobility change to electron transfer and intervalley scattering.[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8) Strained-Si devices grew out of early-1980s work on Si layers on SiGe buffers, which showed enhanced electron mobilities in Si/Si\\(_{1-x}\\)Ge\\(_x\\) heterostructures.[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8) • [16](https://link.springer.com/book/10.1007/978-1-4419-0552-9) D. K. Nayak and colleagues reported a high-mobility p-channel MOSFET on strained Si in [Applied Physics Letters](https://www.edgepedia.org/applied-physics-letters) in 1993,[17](https://doi.org/10.1063/1.109205) and high-stress capping layers on MOSFETs appeared in the late 1990s, activating uniaxial stress for production.[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8) The general framework of \"elastic strain engineering\" was put forward by [Ju Li](https://www.edgepedia.org/ju-li), Zhiwei Shan, and Evan Ma in MRS Bulletin in 2014.[18](https://doi.org/10.1557/mrs.2014.3)\n\n## Variants\n\n**Biaxial versus uniaxial.** Process-induced uniaxial stress is the form used in modern production CMOS, because it gives larger mobility enhancement and smaller threshold-voltage shifts than biaxial stress; it produced an approximately five times smaller n-channel threshold-voltage shift than biaxial substrate strain.[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8) • [16](https://link.springer.com/book/10.1007/978-1-4419-0552-9) Uniaxial strain is also more efficient: only 0.2% lattice displacement is needed for a 30% mobility gain, versus a larger displacement in the biaxial case.[4](https://web.stanford.edu/class/ee311/NOTES/Intel%20Strain%20Si%20EDL04.pdf)\n\n**Pseudomorphic growth and relaxed templates.** In coherent epitaxy the film's parallel lattice parameter equals the substrate's, giving tetragonal distortion \\( \\epsilon = (a_{\\parallel} - a_{\\mathrm{film}})/a_{\\mathrm{film}} \\); if the stored elastic energy exceeds the defect formation energy, misfit dislocations form.[19](https://gregorykimball.me/wp-content/uploads/2012/03/2011-leitewarmannkimball-wafer_scale_strain_engineering_of_ultrathin.pdf) By 1989, high-quality strained-layer superlattices of lattice-mismatched semiconductors could be grown, and axial strain was used deliberately to split the light- and heavy-hole degeneracy.[20](https://iopscience.iop.org/article/10.1088/0268-1242/4/3/001/meta)\n\n**Strain in 2D materials.** For 2D semiconductors the same families of methods apply, benchmarked against strained silicon: lattice mismatch, thermal-expansion mismatch, substrate-induced stress, and process-induced stress.[21](https://link.springer.com/article/10.1007/s40843-025-3471-2) A recent variant deposits patterned stressed films on non-twisted 2D layers, generating moiré interference from strain-induced lattice mismatch without twisting or stacking.[22](https://arxiv.org/pdf/2510.13699) Dynamically tunable strain has arrived through surface acoustic waves and time-dependent piezoelectric substrates, which generate effective gauge fields; acoustic waves on LiNbO3 induced a giant synthetic Hall voltage without external magnetic fields.[15](https://google.iopscience.iop.org/article/10.1088/1361-6633/ad06db)\n\n## Applications\n\n**CMOS logic.** Intel's 90 nm technology raised saturated n- and p-type drive currents by 10% and 25%; uniaxial strain increased hole mobility by 50% for a 45-nm gate transistor, and the enhancement persists at high vertical field, unlike biaxial strain.[4](https://web.stanford.edu/class/ee311/NOTES/Intel%20Strain%20Si%20EDL04.pdf) CMOS-compatible strain engineering for monolayer semiconductor transistors was reported in Nature Electronics in 2024 by Marc Jaikissoon and colleagues.[23](https://doi.org/10.1038/s41928-024-01244-7)\n\n**Optoelectronics.** Strain-based valence-band engineering was proposed for high hole mobility transistors and low-threshold, long-wavelength lasers.[20](https://iopscience.iop.org/article/10.1088/0268-1242/4/3/001/meta) A strained WS2 monolayer on porous Si\\(_3\\)N\\(_4\\) reached a phototransistor responsivity of \\( 1.58 \\times 10^{5} \\) A/W with 40 ms response.[7](https://pubs.acs.org/nalefd/article/24/41/12722/149668/Bandgap-Engineering-of-2D-Materials-toward-High)\n\n**2D transistors, thermal control, and design.** About 0.3% biaxial tensile strain on flexible substrates raises WS2 transistor on-current by 1.8 ± 0.4× and mobility by 2.3 ± 0.5×.[24](https://arxiv.org/pdf/2309.10939) Elastic strain also tunes thermal conductivity over an order of magnitude in diamond.[2](http://li.mit.edu/Archive/Papers/24/Shi24TsymbalovPNAS.pdf) Machine learning guides strain design: a framework trained on limited ab initio data predicts band gaps within 8 meV and found indirect-to-direct and semiconductor-to-metal transitions in silicon by scanning the full six-dimensional strain space.[25](https://www.pnas.org/doi/abs/10.1073/pnas.1818555116)\n\n## Limitations and alternatives\n\nRelaxation is the central failure mode. In epitaxy, misfit dislocations form once elastic energy exceeds defect formation energy, compromising devices.[19](https://gregorykimball.me/wp-content/uploads/2012/03/2011-leitewarmannkimball-wafer_scale_strain_engineering_of_ultrathin.pdf) In perfect crystals the reversible elastic limit ends at the ideal strain, beyond which relaxation occurs by phonon instability.[2](http://li.mit.edu/Archive/Papers/24/Shi24TsymbalovPNAS.pdf) Real 2D layers with chalcogen vacancies and grain boundaries fail at about 2 to 4% strain despite calculated fracture strains of 10 to 15% for pristine MoS2.[26](https://onlinelibrary.wiley.com/doi/full/10.1002/advs.75506) Strain transfer is another weak point: above about 1.7% applied strain the MoS2–substrate interaction can break, relaxing the strain and failing the device,[14](https://www.nature.com/articles/s41467-020-15023-3) and the common polymer-substrate approach suffers from weak adhesion that prevents full strain transfer.[15](https://google.iopscience.iop.org/article/10.1088/1361-6633/ad06db) High compressive strain causes early buckling in suspended membranes,[7](https://pubs.acs.org/nalefd/article/24/41/12722/149668/Bandgap-Engineering-of-2D-Materials-toward-High) and large hydrostatic strain is undesirable in CMOS because of strain relaxation, band-gap narrowing, and threshold-voltage shifts.[1](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8)\n\nStrain is positioned as an alternative to chemical doping and quantum confinement for band-gap tuning, working by altering bond lengths and orbital overlap, and as complementary to doping and electrostatic gating; published comparisons are qualitative rather than quantitative head-to-head benchmarks.[7](https://pubs.acs.org/nalefd/article/24/41/12722/149668/Bandgap-Engineering-of-2D-Materials-toward-High) • [3](https://europepmc.org/article/med/35950446)\n\n## References\n\n1. [Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors (Sun, Thompson, Nishida, J. Appl. Phys. review, full text)](https://ptacts.uspto.gov/ptacts/public-informations/petitions/1557982/download-documents?artifactId=-rxXyJNxaRFN6CXV7OwwPEnup1toJN5uzlgQce287j9quMjVFodk7S8)\n2. [Phonon stability boundary and deep elastic strain engineering of lattice thermal conductivity (PNAS, 2024, author-hosted copy)](http://li.mit.edu/Archive/Papers/24/Shi24TsymbalovPNAS.pdf)\n3. [Recent Progress in Strain Engineering on Van der Waals 2D Materials (Advanced Materials, 2023)](https://europepmc.org/article/med/35950446)\n4. [A Logic Nanotechnology Featuring Strained-Silicon (Thompson et al., IEEE Electron Device Letters, 2004)](https://web.stanford.edu/class/ee311/NOTES/Intel%20Strain%20Si%20EDL04.pdf)\n5. [Advancements and challenges in strained group-IV-based optoelectronic materials stressed by ion beam treatment (J. Phys.: Condens. Matter, 2024)](https://iopscience.iop.org/article/10.1088/1361-648X/ad649f)\n6. [Enhancing Carrier Mobility in Monolayer MoS2 Transistors with Process-Induced Strain (ACS Nano, 2024)](https://pubs.acs.org/ancac3/article/18/19/12377/150464/Enhancing-Carrier-Mobility-in-Monolayer-MoS2)\n7. [Bandgap Engineering of 2D Materials toward High-Performing Straintronics (Nano Letters, 2024)](https://pubs.acs.org/nalefd/article/24/41/12722/149668/Bandgap-Engineering-of-2D-Materials-toward-High)\n8. [Effect of Strain on the Band Gap of Monolayer MoS2 (Physical Review B 110, 144109; arXiv:2406.06020)](https://link.aps.org/accepted/10.1103/PhysRevB.110.144109)\n9. [Strain engineering of 2D semiconductors and graphene: from strain fields to band-structure tuning and photonic applications (Light: Science & Applications, 2020)](https://www.nature.com/articles/s41377-020-00421-5)\n10. [J. Bardeen, W. Shockley (1950). Deformation Potentials and Mobilities in Non-Polar Crystals. Physical Review.](https://doi.org/10.1103/physrev.80.72)\n11. [Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs (Chu, Sun, Aghoram, Thompson, Annu. Rev. Mater. Res. 39, 2009)](https://www.annualreviews.org/content/journals/10.1146/annurev-matsci-082908-145312)\n12. [Strain engineering in 2D FETs: Physics, status, and prospects (Journal of Applied Physics, 2024)](https://pubs.aip.org/aip/jap/article/136/9/090901/3311660/Strain-engineering-in-2D-FETs-Physics-status-and)\n13. [Efficient and anisotropic strain engineering in few-layer 3R-MoS2 via polymer encapsulation (Applied Physics Letters, 2026)](https://pubs.aip.org/aip/apl/article/128/25/251107/3396330/Efficient-and-anisotropic-strain-engineering-in)\n14. [Efficient strain modulation of 2D materials via polymer encapsulation (Nature Communications, 2020)](https://www.nature.com/articles/s41467-020-15023-3)\n15. [Mechanical, electronic, optical, piezoelectric and ferroic properties of strained graphene and other strained monolayers and multilayers: an update (Reports on Progress in Physics, 2023)](https://google.iopscience.iop.org/article/10.1088/1361-6633/ad06db)\n16. [Strain Effect in Semiconductors: Theory and Device Applications (Sun, Thompson, Nishida, Springer, 2010)](https://link.springer.com/book/10.1007/978-1-4419-0552-9)\n17. [D. K. Nayak and colleagues (1993). High-mobility p-channel metal-oxide-semiconductor field-effect transistor on strained Si. Applied Physics Letters.](https://doi.org/10.1063/1.109205)\n18. [Ju Li, Zhiwei Shan, Evan Ma (2014). Elastic strain engineering for unprecedented materials properties. MRS Bulletin.](https://doi.org/10.1557/mrs.2014.3)\n19. [Wafer-Scale Strain Engineering of Ultrathin Semiconductor Crystalline Layers (Adv. Mater., 2011, DOI 10.1002/adma.201101309; author-hosted copy)](https://gregorykimball.me/wp-content/uploads/2012/03/2011-leitewarmannkimball-wafer_scale_strain_engineering_of_ultrathin.pdf)\n20. [Valence band engineering in strained-layer structures (O'Reilly, Semicond. Sci. Technol. 4, 121, 1989)](https://iopscience.iop.org/article/10.1088/0268-1242/4/3/001/meta)\n21. [Strain technology of two-dimensional semiconductors for industrial electronics (Science China Materials, 2025)](https://link.springer.com/article/10.1007/s40843-025-3471-2)\n22. [Strain-induced Moiré Reconstruction and Memorization in Two-Dimensional Materials without Twist (arXiv, 2025)](https://arxiv.org/pdf/2510.13699)\n23. [Marc Jaikissoon and colleagues (2024). CMOS-compatible strain engineering for monolayer semiconductor transistors. Nature Electronics.](https://doi.org/10.1038/s41928-024-01244-7)\n24. [Biaxial Tensile Strain Enhances Electron Mobility of Monolayer Transition Metal Dichalcogenides (ACS Nano 2024; arXiv preprint copy)](https://arxiv.org/pdf/2309.10939)\n25. [Deep elastic strain engineering of bandgap through machine learning (PNAS, 2019)](https://www.pnas.org/doi/abs/10.1073/pnas.1818555116)\n26. [Progress in Strain Engineering of 2D-Integrated Heterostructures for Ultrasensitive Sensors (Advanced Science, Wiley, 2026)](https://onlinelibrary.wiley.com/doi/full/10.1002/advs.75506)\n\n---\n*Topic: Encyclopedia › Technology and the built world › Engineering and manufacturing › Materials science and metallurgy*\n\n*Initially written Sep 29, 2026 · Reviewed: Sep 30, 2026 · Edited: Sep 30, 2026 · Last review: Sep 30, 2026*\n\n*Copyright 2026 EdgeChat AI, a subsidiary of Biostate AI.*\n\nLicense: Edgepedia Community License 1.0, https://www.edgepedia.org/edgepedia/license\n", "same_as": [], "url": "https://www.edgepedia.org/strain-engineering", "markdown_url": "https://www.edgepedia.org/strain-engineering.md", "license": { "name": "Edgepedia Community License 1.0", "url": "https://www.edgepedia.org/edgepedia/license", "summary": "Free with credit, commercial use included. AI training is open to everyone. For other uses, organizations over USD 100M in revenue or 100M monthly users license separately.", "spdx": "LicenseRef-Edgepedia-Community-1.0" }, "credit": "\"Strain engineering\", Edgepedia (EdgeChat), https://www.edgepedia.org/strain-engineering. Edgepedia Community License 1.0.", "credit_md": "\"[Strain engineering](https://www.edgepedia.org/strain-engineering)\", Edgepedia (EdgeChat), [https://www.edgepedia.org/strain-engineering](https://www.edgepedia.org/strain-engineering). [Edgepedia Community License 1.0](https://www.edgepedia.org/edgepedia/license).", "credit_html": "\"Strain engineering\", Edgepedia (EdgeChat), https://www.edgepedia.org/strain-engineering. Edgepedia Community License 1.0.", "speakable": "Strain engineering deliberately applies elastic strain to crystals or thin films to change their properties; strained silicon became standard in 90, 65, and 45 nm CMOS logic." }