# ARM Cortex-A725
**ARM Cortex-A725** is an out-of-order CPU core from Arm, announced on May 29, 2024 as the second-generation Armv9.2 successor to the Cortex-A720 in the Cortex-A700 series.[1](https://newsroom.arm.com/blog/armv9-cpus-consumer-devices) Arm positions it as the "workhorse" core for sustained CPU workloads in mobile devices that must balance gaming, web browsing, and AI processing within a constrained power envelope.[1](https://newsroom.arm.com/blog/armv9-cpus-consumer-devices) • [2](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725)
| Key fact | Detail |
|---|---|
| Architecture | Armv9.2-A, AArch64-only at all exception levels EL0 to EL3[2](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725) • [3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) |
| Gains over Cortex-A720 | 25% greater power efficiency, 35% performance efficiency, and 12% more performance[1](https://newsroom.arm.com/blog/armv9-cpus-consumer-devices) • [2](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725) |
| Execution | Out-of-order, 13 issue pipelines, one micro-operation per pipeline per cycle[4](https://documentation-service.arm.com/static/6749c761c7fc0d1f211dc2f9) |
| Caches | L1 instruction and data caches of 32KB or 64KB (4-way, 64-byte lines); private 8-way L2 of 128KB, 256KB, 512KB, or 1024KB[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) |
| Vector support | SVE and SVE2 with a 128-bit vector length; optional Cryptographic Extension under separate license[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) |
| Cluster | Implemented inside a DynamIQ Shared Unit-120 (DSU-120), combinable with Cortex-X925 and Cortex-A520 in big.LITTLE configurations[2](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725) • [3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) |
| Notable implementations | MediaTek Dimensity 8400 (8 cores up to 3.25GHz), Google Tensor G5 (5 cores at 3.05GHz), NVIDIA GB10 (10 cores)[5](https://www.mediatek.com/press-room/mediatek-unveils-the-dimensity-8400-the-first-all-big-core-chip-for-premium-smartphones?hs_amp=true) • [6](https://www.androidcentral.com/phones/google-pixel/google-tensor-g5) • [7](https://www.techradar.com/computing/acer-veriton-gn100-ai-mini-pc-workstation-review) |
## Positioning and performance claims
The Cortex-A725 sits between the Cortex-X925 performance core and the Cortex-A520 efficiency core in Arm's 2024 Armv9.2 lineup. Arm describes the division of labor in a cluster this way: Cortex-X925 handles bursty workloads such as application launches and web browsing, Cortex-A725 provides the sustained performance required for common AI workloads and AAA gaming, and Cortex-A520 covers light media and background tasks.[1](https://newsroom.arm.com/blog/armv9-cpus-consumer-devices)
Arm's launch claims quantify the step from the Cortex-A720: a 35 percent improvement in performance efficiency and a 25 percent improvement in power efficiency, attributed to microarchitecture changes.[1](https://newsroom.arm.com/blog/armv9-cpus-consumer-devices) The product page states the same efficiency figure alongside 12 percent more raw performance.[2](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725) Coverage of the launch also cites a 20 percent reduction in L3 traffic compared with the A720, which reduces energy spent on memory access.[8](https://www.cnx-software.com/2024/05/30/arm-cortex-x925-cortex-a725-cpus-immortalis-g925-gpu-kleidi-ai-software/?amp=1)
## Microarchitecture
The core implements the Armv9.2-A A64 instruction set, which extends the Armv8-A architecture up to Armv8.7-A, and executes in the AArch64 state at all exception levels.[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) • [4](https://documentation-service.arm.com/static/6749c761c7fc0d1f211dc2f9) Instructions are fetched and decoded into macro-operations, renamed, and dispatched; a macro-operation can be split into two micro-operations, which issue out-of-order to one of thirteen issue pipelines.[4](https://documentation-service.arm.com/static/6749c761c7fc0d1f211dc2f9)
**Memory system.** The L1 instruction and data caches are each 32KB or 64KB, 4-way set associative with 64-byte lines, and the L1 data TLB natively supports 4KB, 16KB, 64KB, and 2MB page sizes.[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) The private L2 cache is 8-way set associative and configurable at 128KB, 256KB, 512KB, or 1024KB; Arm's product page notes that the L2 can be double the Cortex-A720's size, contributing to system-level power savings together with the refreshed DSU-120.[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) • [2](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725)
**Vector and security features.** The core supports the [Scalable Vector Extension](https://www.edgepedia.org/scalable-vector-extension) and SVE2 with a 128-bit vector length, complementing the Advanced SIMD and floating-point units.[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) The Cryptographic Extension, which accelerates AES, SHA-1, SHA-2, SHA-3, SM3, SM4, and finite-field arithmetic, is optional and supplied only under an additional license beyond the core license.[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) The core also implements the RAS (Reliability, [Availability](https://www.edgepedia.org/availability), and Serviceability) Extension, Memory Tagging Extensions, and QARMA3 pointer authentication per Arm's comparison table.[9](https://documentation-service.arm.com/static/6659aff18ad83c4754308694%3Ftoken%3D)
## Cluster integration
The Cortex-A725 is implemented inside a DynamIQ Shared Unit-120 cluster, which behaves as a full interconnect with shared L3 cache and snoop control; all external interfaces to the SoC are managed through the DSU-120.[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5) The DSU-120 supports 1 to 14 cores of up to three types and an optional L3 cache from 0KB to 32MB, so a cluster can combine Cortex-X925, Cortex-A725, and Cortex-A520 cores in a single big.LITTLE configuration.[10](https://support.arm.com/compute-ip/dsu-120) • [2](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725) Each core connects to the DSU-120 through an asynchronous CPU bridge, allowing different clock frequencies between core and cluster.[3](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5)
Arm offers an optimized 3nm physical implementation of the Cortex-A725 through its advanced physical implementation program, alongside an area-optimized implementation for mainstream consumer markets.[1](https://newsroom.arm.com/blog/armv9-cpus-consumer-devices)
## Implementations
The core appeared in consumer silicon from late 2024 onward:
- **MediaTek Dimensity 8400** (announced December 23, 2024) uses an eight-core all-big-core CPU of Cortex-A725 cores at up to 3.25GHz, with 1MB, 512KB, and 256KB L2 tiers, claiming 41% higher multi-core performance and 44% lower peak power than the Dimensity 8300.[5](https://www.mediatek.com/press-room/mediatek-unveils-the-dimensity-8400-the-first-all-big-core-chip-for-premium-smartphones?hs_amp=true) • [11](https://www.mediatek.com/products/smartphones/mediatek-dimensity-8400) The Dimensity 8500-Ultra in the [Xiaomi 17T](https://www.edgepedia.org/xiaomi-17t) runs A725 cores up to 3.4GHz.[12](https://www.mi.com/global/product/xiaomi-17t/specs/)
- **Google Tensor G5** ([Pixel 10](https://www.edgepedia.org/pixel-10), 2025) pairs one Cortex-X4 at 3.78GHz with five Cortex-A725 cores at 3.05GHz and two Cortex-A520 cores at 2.25GHz, manufactured on TSMC 3nm.[6](https://www.androidcentral.com/phones/google-pixel/google-tensor-g5)
- **NVIDIA GB10** (Project DIGITS / DGX Spark-class systems) combines 10 Cortex-X925 and 10 Cortex-A725 cores under the Armv9.2-A architecture.[7](https://www.techradar.com/computing/acer-veriton-gn100-ai-mini-pc-workstation-review)
## Successor
Arm's C1 CPU cluster generation introduced the C1-Pro core, which the company says maintains similar performance on SPEC benchmark suites at a much smaller area footprint and is up to 12 percent more power efficient than the Cortex-A725 at the same performance for video, web browsing, and social media use cases.[13](https://newsroom.arm.com/blog/arm-c1-cpu-cluster-on-device-ai-performance)
## References
1. [New Armv9 CPUs for Accelerating AI on Mobile and Beyond, Arm Newsroom (May 29, 2024)](https://newsroom.arm.com/blog/armv9-cpus-consumer-devices)
2. [Cortex-A725 product page, Arm](https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a725)
3. [Arm Cortex-A725 Core Technical Reference Manual, Arm](https://documentation-service.arm.com/static/665741a0876c8d213b785bf5)
4. [Arm Cortex-A725 Core Software Optimization Guide, Arm](https://documentation-service.arm.com/static/6749c761c7fc0d1f211dc2f9)
5. [MediaTek unveils the Dimensity 8400 (December 23, 2024), MediaTek press room](https://www.mediatek.com/press-room/mediatek-unveils-the-dimensity-8400-the-first-all-big-core-chip-for-premium-smartphones?hs_amp=true)
6. [Google Tensor G5: Benchmarks and everything you need to know, Android Central](https://www.androidcentral.com/phones/google-pixel/google-tensor-g5)
7. [Acer Veriton GN100 AI mini PC workstation review, TechRadar](https://www.techradar.com/computing/acer-veriton-gn100-ai-mini-pc-workstation-review)
8. [Arm unveils Cortex-X925 and Cortex-A725 CPUs, Immortalis-G925 GPU, Kleidi AI software, CNX Software (May 30, 2024)](https://www.cnx-software.com/2024/05/30/arm-cortex-x925-cortex-a725-cpus-immortalis-g925-gpu-kleidi-ai-software/?amp=1)
9. [Arm Cortex-A Processor Comparison Table, Arm](https://documentation-service.arm.com/static/6659aff18ad83c4754308694%3Ftoken%3D)
10. [DynamIQ Shared Unit 120 Product Support, Arm](https://support.arm.com/compute-ip/dsu-120)
11. [MediaTek Dimensity 8400 product page, MediaTek](https://www.mediatek.com/products/smartphones/mediatek-dimensity-8400)
12. [Xiaomi 17T specifications, Xiaomi](https://www.mi.com/global/product/xiaomi-17t/specs/)
13. [Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster, Arm Newsroom](https://newsroom.arm.com/blog/arm-c1-cpu-cluster-on-device-ai-performance)
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*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Computer hardware › Processors & processor engineering › Microarchitecture & implementation › Apple silicon microarchitectures*
*Initially written Sep 17, 2026 · Reviewed: Sep 30, 2026; Oct 15, 2026 · Edited: Sep 30, 2026; Oct 11, 2026; Oct 15, 2026 · Last review: Oct 15, 2026*
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License: Edgepedia Community License 1.0, https://www.edgepedia.org/edgepedia/license