# Branch (computer science)
A branch in computer science is an instruction that transfers control to a different point in a program instead of continuing sequentially, and it is the mechanism behind loops, decisions, and function calls. Branches appear at every level of the machine: as instructions in an instruction set, as edges in a compiler's control flow graph, and as events that a processor's branch predictor must guess in advance to keep its pipeline full.
| Key fact | Detail |
|---|---|
| Basic instruction types | Unconditional jumps and conditional branches; RV32I provides exactly these two types of control transfer instructions[1](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf) |
| Direct vs indirect | Direct branches encode an offset in the instruction itself; indirect branches take their target from a register, as in ARM's BR [1](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf) • [2](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20Instruction%20Set%20Architecture.pdf?revision=ebf53406-04fd-4c67-a485-1b329febfb3e) |
| Reach limits | RISC-V conditional branches reach ±4 KiB and JAL jumps ±1 MiB; A64 conditional branches reach ±1 MB and unconditional B branches ±128 MB[1](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf) • [2](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20Instruction%20Set%20Architecture.pdf?revision=ebf53406-04fd-4c67-a485-1b329febfb3e) |
| Compiler role | Branches end basic blocks; a control flow graph has basic blocks as nodes and branches as edges[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html) |
| Loop detection | A cycle in the flow graph is a loop only if it has a single-entry header; back edges are arcs whose head dominates their tail[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html) |
| Execution cost | Mispredicted branches delay instructions, trigger pipeline flushes, and reduce speculation efficiency[4](https://arxiv.org/abs/1906.08170) |
| Security impact | Spectre attacks use branch prediction and speculative execution to leak a victim's confidential information through side channels[5](https://arxiv.org/abs/1801.01203) |
## Branch instructions in an instruction set
Instruction sets divide control transfer instructions into two families. RISC-V's RV32I base provides unconditional jumps and conditional branches, and its designers note that control transfer instructions in RV32I have no architecturally visible delay slots[1](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf). A conditional branch tests a condition and transfers control only when it holds; an unconditional jump always transfers.
**Direct and indirect targets.** A direct branch encodes its destination as an offset within the instruction. RISC-V conditional branches use the B-type format with a 12-bit immediate encoding signed offsets in multiples of 2 bytes, giving a ±4 KiB range, while the JAL jump reaches ±1 MiB[1](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf). Arm's A64 set is similar in shape: the conditional B. instruction has a ±1 MB range because some bits must store the condition itself, while the unconditional B instruction reaches ±128 MB[2](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20Instruction%20Set%20Architecture.pdf?revision=ebf53406-04fd-4c67-a485-1b329febfb3e). An indirect branch instead takes its target from a register: A64's BR performs an absolute branch to the address in Xn[2](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20Instruction%20Set%20Architecture.pdf?revision=ebf53406-04fd-4c67-a485-1b329febfb3e), and RISC-V's JALR adds a 12-bit immediate to the value in rs1[1](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf). Indirect branches serve function pointers, virtual dispatch, switch dispatch, and returns.
The direct encoding has a security consequence: because the target is fixed in the instruction, direct branches are not susceptible to control-flow subversion, the attack style in which an adversary diverts a control transfer instruction such as JALR or C.JR to a new target by corrupting a return stack or memory[1](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf).
## Branches in compilers: basic blocks and the control flow graph
Compilers analyze branches by partitioning a program into basic blocks. A basic block is a sequence of intermediate-representation instructions that allows no flow of control in or out of the block except at the top or bottom[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html). Once a block is entered, every instruction in it executes in order, so analysis inside a block is straight-line reasoning; all the difficulty of control flow is concentrated in the edges between blocks[6](https://www.nexous.in/compilers/intermediate-code/basic-blocks).
**Finding the blocks.** Blocks are delimited by leaders, the first instructions of blocks. Three rules identify them: the first statement of the program or procedure, the target of a branch (usually marked by a label), and the statement immediately after a conditional or unconditional branch, since after a branch control either continues there or does not[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html). Each leader owns everything up to the next leader, and a block can be a single instruction if the rules say so[6](https://www.nexous.in/compilers/intermediate-code/basic-blocks).
**Building the graph.** Joining the blocks by their possible transfers of control yields the control flow graph, a directed graph whose nodes are basic blocks and whose edges are determined by the places where the nodes branch[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html). A block ending in a conditional branch has two outgoing edges, labeled for the true and false outcomes; other blocks have a single departing arrow[7](https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c11/c11s1/). In intermediate representations such as [LLVM IR](https://www.edgepedia.org/llvm-ir), every basic block must end with a terminator instruction such as a branch or return, and the function's list of blocks forms its CFG[8](https://www.llvm.org/docs/LangRef.html).
**Loops.** A cycle in the flow graph is a loop, and the compiler never needed to be told there was a for in the source; it would find the same cycle in code written with raw gotos[6](https://www.nexous.in/compilers/intermediate-code/basic-blocks). For optimization purposes a stricter definition applies: a cycle must have a header, a node that every path from the start node to the cycle passes through, to be considered a loop, because code motion cannot be done safely if there is more than one entry to the loop[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html). Algorithms find loops via dominators, depth-first search, and back edges, arcs whose head dominates their tail[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html). The payoff is high because programs spend the bulk of their time in loops, where optimizations such as loop-invariant code motion apply[3](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html).
## Branches in processors: prediction and speculation
A pipelined processor must fetch the next instruction before it has evaluated the current branch, so the branch creates a control hazard. The standard remedy is to guess. [Branch prediction](https://www.edgepedia.org/branch-prediction) units train statistical models of branch directions as instructions retire and use those models to predict unresolved branches as they are fetched; the predictions drive speculative execution, a key technique for hiding latency in out-of-order CPUs[4](https://arxiv.org/abs/1906.08170). When a prediction is wrong, the pipeline must be flushed and restarted on the correct path[9](https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c15/c15s1/).
Modern predictors are highly accurate on most branches, but the residual errors matter. A measurement study of the state-of-the-art TAGE-SC-L predictor found that correcting its mispredictions on SPECint 2017 would improve instructions per cycle by margins similar to an advance in process technology node, and that the mispredictions arise from a small number of systematically hard-to-predict branches or from rare branches with low dynamic execution counts[4](https://arxiv.org/abs/1906.08170).
**Removing branches instead of predicting them.** Compilers can also eliminate a branch. LLVM's if-conversion pass converts conditional branches into predicated instructions, executing instructions from both sides of the branch and selecting the result with a conditional move[10](https://llvm.org/doxygen/IfConversion_8cpp_source.html) • [11](https://llvm.org/doxygen/EarlyIfConversion_8cpp_source.html). This trades a possible misprediction penalty for guaranteed work on both paths, and it is profitable only when the branch is hard to predict or the converted region is small.
## Security
[Speculative execution](https://www.edgepedia.org/speculative-execution) leaves microarchitectural traces even when the speculative instructions are discarded. Spectre attacks induce a victim to speculatively perform operations that would not occur during correct program execution and to leak the victim's confidential information via a side channel to the adversary; the paper demonstrating them showed that speculative execution violates the security assumptions behind operating system process separation, containerization, and just-in-time compilation, and that vulnerable speculative execution is found in microprocessors from Intel, AMD, and ARM used in billions of devices[5](https://arxiv.org/abs/1801.01203). Because the attacks misguide the branch prediction structures themselves, mitigations include control-flow integrity techniques applied to the committed path to prevent speculative control flow from being hijacked[12](https://arxiv.org/abs/1906.01345).
## References
1. [The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, RISC-V International](https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf)
2. [Armv8-A Instruction Set Architecture, Arm Limited](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20Instruction%20Set%20Architecture.pdf?revision=ebf53406-04fd-4c67-a485-1b329febfb3e)
3. [PLT Module 7: Control Flow Analysis, WPI](https://web.cs.wpi.edu/~kal/courses/compilers/module7/mycfa.html)
4. [Lin, C.-K. and Tarsa, S. J. (2019). Branch Prediction Is Not a Solved Problem: Measurements, Opportunities, and Future Directions. arXiv.](https://arxiv.org/abs/1906.08170)
5. [Kocher, P. et al. (2018). Spectre Attacks: Exploiting Speculative Execution. arXiv.](https://arxiv.org/abs/1801.01203)
6. [Basic Blocks and Flow Graphs, Compiler Design, Nexous](https://www.nexous.in/compilers/intermediate-code/basic-blocks)
7. [Computation Structures, 11.1 Annotated Slides, MIT OpenCourseWare](https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c11/c11s1/)
8. [LLVM Language Reference Manual, LLVM Project](https://www.llvm.org/docs/LangRef.html)
9. [Computation Structures, 15.1 Annotated Slides, MIT OpenCourseWare](https://ocw.mit.edu/courses/6-004-computation-structures-spring-2017/pages/c15/c15s1/)
10. [IfConversion.cpp, LLVM Project source](https://llvm.org/doxygen/IfConversion_8cpp_source.html)
11. [EarlyIfConversion.cpp, LLVM Project source](https://llvm.org/doxygen/EarlyIfConversion_8cpp_source.html)
12. [SPECCFI: Mitigating Spectre Attacks using CFI Informed Speculation. arXiv.](https://arxiv.org/abs/1906.01345)
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*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Computer hardware › Processors & processor engineering › Computer architecture theory*
*Initially written Sep 17, 2026 · Reviewed: Oct 15, 2026 · Edited: Oct 15, 2026 · Last review: Oct 15, 2026*
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