# DDR3 SDRAM
**DDR3 SDRAM** (Double Data Rate 3 Synchronous Dynamic Random-Access Memory) is a generation of the [DDR SDRAM](https://www.edgepedia.org/ddr-sdram) computer-memory standard, defined by JEDEC in specification JESD79-3 and first released as a standard on September 1, 2007[1](https://standards.globalspec.com/std/1539317/jedec-jesd-79-3). It succeeded [DDR2 SDRAM](https://www.edgepedia.org/ddr2-sdram), running at data rates from 800 to 2133 megatransfers per second (MT/s) at a nominal supply voltage of 1.5 V, with a low-voltage variant (DDR3L) at 1.35 V[2](https://support.visiontek.com/hc/en-us/articles/31176771882387-What-are-the-key-differences-between-DDR2-DDR3-DDR4-and-DDR5-memory) • [3](https://www.micron.com/products/memory/dram-components/ddr3-to-ddr4). It was widely used in desktop, laptop, consumer-electronics, automotive, and medical systems[4](https://semiconductor.samsung.com/kr/dram/ddr/ddr3/).
| Key fact | Detail |
|---|---|
| Standard | JEDEC JESD79-3, first published September 1, 2007; covers 512 Mb through 8 Gb devices in x4, x8, and x16 configurations[1](https://standards.globalspec.com/std/1539317/jedec-jesd-79-3) |
| Prefetch architecture | 8n-prefetch; the interface transfers two data words per clock cycle at the I/O pins[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf) |
| Data rates | 800, 1066, 1333, 1600, 1866, 2133 MT/s[3](https://www.micron.com/products/memory/dram-components/ddr3-to-ddr4) |
| Voltage | 1.5 V nominal (±0.075 V); DDR3L low-voltage standard at 1.35 V[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf) • [3](https://www.micron.com/products/memory/dram-components/ddr3-to-ddr4) |
| Module formats | 240-pin DIMM (desktop) and 204-pin SODIMM (laptop)[2](https://support.visiontek.com/hc/en-us/articles/31176771882387-What-are-the-key-differences-between-DDR2-DDR3-DDR4-and-DDR5-memory) |
| Latency settings | CAS read latency (CL) of 5, 6, 7, 8, 9, 10, or 11; CAS write latency (CWL) of 5, 6, 7, or 8[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf) |
| Successor | DDR4 SDRAM, introduced 2014, at 1.2 V and data rates of 1600 to 3200 MT/s[2](https://support.visiontek.com/hc/en-us/articles/31176771882387-What-are-the-key-differences-between-DDR2-DDR3-DDR4-and-DDR5-memory) |
## Architecture
DDR3 achieves high-speed operation through a double data rate architecture with an 8n-prefetch design. Each read or write operation involves one 8n-bit-wide transfer lasting a full clock cycle within the DRAM core, paired with eight matching n-bit-wide transfers of half a clock cycle each at the I/O pins, meaning the interface delivers two data words per clock cycle.[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf) The device operates from a differential clock (CK and CK#); control, command, and address signals are registered at every positive edge of CK[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf).
A differential data strobe (DQS, DQS#) is transmitted externally along with the data for use in capture at the input receiver. DQS is center-aligned with data for writes, while read data transmitted by the device is edge-aligned to the strobes[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf).
**Banks and bursts.** A Micron 1 Gb DDR3 component contains 8 internal banks, and read and write accesses are burst-oriented, using a fixed burst length of 8 (BL8) or a burst chop of 4 (BC4)[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf). An access begins with an ACTIVATE command, whose address bits select the bank and row, followed by a READ or WRITE command, whose address bits select the bank and starting column[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf). An auto precharge function can be enabled to provide a self-timed row precharge initiated at the end of the burst access[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf). As with earlier DDR SDRAM, the pipelined, multibank architecture allows concurrent operation, providing high bandwidth by hiding row precharge and activation time[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf).
The device also provides nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals, which places termination resistance internal to the chip rather than on the module[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf).
## Timing parameters
Access timing is described by a set of standard parameters. tRCD is the RAS-to-CAS delay, the time from an ACTIVATE command that opens a row to a READ or WRITE command; tRC is the row cycle time, the minimum time between ACTIVATE commands to the same bank, defined as tRC = tRAS + tRP[6](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-21/GUID-A29420D1-4E36-4920-B9BB-DD0B63F5E787.html). [CAS latency](https://www.edgepedia.org/cas-latency) (CL), the number of clock cycles between a column address and the start of the returned data, is the most commonly quoted timing parameter[7](https://www.techradar.com/computing/computing-components/what-is-cas-latency-in-ram). DDR3 modules are conventionally labeled with a CL-tRCD-tRP triple such as 7-7-7, 9-9-9, or 11-11-11, expressed in clock cycles[8](https://www.mouser.com/pdfdocs/DDR3DRAMRevD.PDF).
## History and adoption
Samsung states that it developed DDR3 in 2005, the first in the industry[4](https://semiconductor.samsung.com/kr/dram/ddr/ddr3/), and its history page records the development of the industry's first DDR3 SDRAM[9](https://semiconductor.samsung.com/about-us/history/). JEDEC completed the DDR3 SDRAM standard in 2007 and held a DDR3 technical workshop in [San Jose, California](https://www.edgepedia.org/san-jose-california), on October 3–4, 2007[10](https://cdrinfo.com/d7/content/jedec-completes-ddr3-sdram-standard).
Early components doubled the interface speed relative to DDR2: Micron's first DDR3 products supported data rates of 800 to 1066 MT/s with clock frequencies of 400 to 533 MHz, in x4, x8, and x16 output configurations compliant with the JEDEC DDR3 specifications[11](https://investors.micron.com/node/20536/pdf). At launch, sales were not expected to overtake DDR2 until the end of 2009 or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the roll-out in August 2008[12](https://data.kemt.fei.tuke.sk/Architektury_pocitacovych_systemov/_materialy/prednasky/Dynamic%20RAMs.pdf).
Module naming follows the PC3 convention introduced with the DDR generations: DDR3-800 modules are sold as PC3-6400, indicating a peak transfer rate of 6400 MB/sec[13](https://www.dosdays.co.uk/topics/memory.php).
## Voltage and power
The nominal supply is VDD = VDDQ = 1.5 V ±0.075 V, with 1.5 V center-terminated push/pull I/O[5](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf). Intel documents 1.5 V as the recommended and default setting for DDR3 memory voltage on its desktop boards; other BIOS voltage settings are provided for performance tuning only, and changing the voltage can reduce system stability, component life, and data integrity[14](https://www.intel.com/content/www/us/en/support/articles/000007106/boards-and-kits/desktop-boards.html).
The DDR3L low-voltage standard operates at 1.35 V; Micron's product catalog lists DDR3 components at both 1.35 V and 1.5 V I/O voltage[3](https://www.micron.com/products/memory/dram-components/ddr3-to-ddr4) • [15](https://www.micron.com/products/memory/dram-components/ddr3-sdram). Reduced-voltage operation has been studied academically: an experimental study of 124 DDR3L chips from three major vendors found that errors at reduced voltage can be avoided by increasing the latency of activation, restoration, and precharge operations[16](https://arxiv.org/abs/1705.10292).
## Comparison with DDR2, DDR4, and DDR5
DDR3 sits between DDR2 (introduced 2003, 1.8 V, 400 to 1066 MHz, 240-pin DIMM and 200-pin SODIMM) and DDR4 (introduced 2014, 1.2 V, 1600 to 3200+ MHz, 288-pin DIMM and 260-pin SODIMM)[2](https://support.visiontek.com/hc/en-us/articles/31176771882387-What-are-the-key-differences-between-DDR2-DDR3-DDR4-and-DDR5-memory). Relative to DDR2, DDR3 offers higher speeds, lower power consumption, and lower latency[2](https://support.visiontek.com/hc/en-us/articles/31176771882387-What-are-the-key-differences-between-DDR2-DDR3-DDR4-and-DDR5-memory).
Micron's DDR3-to-DDR4 comparison highlights the interface changes: DDR4 drops the core voltage from 1.5 V to 1.2 V, reduces VREF inputs from two (DQ and command/address) to one (command/address only) by making VREFDQ internal, and has no low-voltage standard counterpart to DDR3L[3](https://www.micron.com/products/memory/dram-components/ddr3-to-ddr4). DDR4 also removed the internal word-line charge pumps that DDR3 and earlier generations used, replacing them with a separate VPP supply[17](https://www.micron.com/sales-support/sales/faqs). DDR5, introduced in 2020, doubles the prefetch to 16n to keep the internal core clock low and adds per-bank-group precharge commands[18](https://www.micron.com/products/memory/dram-components/ddr5-sdram).
DDR3 modules are not compatible with other generations; modules of different DDR generations cannot be interchanged, and the key notch position and pin count differ between them[19](https://test.crucial.com/articles/about-memory/is-my-ram-compatible-with-my-motherboard).
## References
1. [JEDEC JESD 79-3 – DDR3 SDRAM Specification, GlobalSpec](https://standards.globalspec.com/std/1539317/jedec-jesd-79-3)
2. [What are the key differences between DDR2, DDR3, DDR4, and DDR5 memory? – VisionTek Products](https://support.visiontek.com/hc/en-us/articles/31176771882387-What-are-the-key-differences-between-DDR2-DDR3-DDR4-and-DDR5-memory)
3. [DDR3 to DDR4 memory, Micron Technology Inc.](https://www.micron.com/products/memory/dram-components/ddr3-to-ddr4)
4. [DDR3 | DRAM, Samsung Semiconductor](https://semiconductor.samsung.com/kr/dram/ddr/ddr3/)
5. [DDR3 SDRAM x4, x8, x16 Component Data Sheet, Micron Technology](https://www.micron-electronic.com/pdf-bb/mt41j64m16jt-15e-ait-g.pdf)
6. [DDR Memory Timing tab, Microchip online documentation](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-21/GUID-A29420D1-4E36-4920-B9BB-DD0B63F5E787.html)
7. [What is CAS latency in RAM? Memory timings and their importance, TechRadar](https://www.techradar.com/computing/computing-components/what-is-cas-latency-in-ram)
8. [DDR3 SDRAM datasheet, Mouser Electronics](https://www.mouser.com/pdfdocs/DDR3DRAMRevD.PDF)
9. [History, Samsung Semiconductor Global](https://semiconductor.samsung.com/about-us/history/)
10. [JEDEC Completes DDR3 SDRAM Standard, CdrInfo.com](https://cdrinfo.com/d7/content/jedec-completes-ddr3-sdram-standard)
11. [Micron Technology's DDR3 Memory for High-End Computing is Validated with Intel Platforms, Micron investors](https://investors.micron.com/node/20536/pdf)
12. [Development and market penetration, Dynamic RAMs lecture material](https://data.kemt.fei.tuke.sk/Architektury_pocitacovych_systemov/_materialy/prednasky/Dynamic%20RAMs.pdf)
13. [DOS Days – Memory](https://www.dosdays.co.uk/topics/memory.php)
14. [DDR3 Memory Voltage Requirements, Intel](https://www.intel.com/content/www/us/en/support/articles/000007106/boards-and-kits/desktop-boards.html)
15. [DDR3 SDRAM products, Micron Technology Inc.](https://www.micron.com/products/memory/dram-components/ddr3-sdram)
16. [Understanding Reduced-Voltage Operation in Modern DRAM Chips, arXiv](https://arxiv.org/abs/1705.10292)
17. [FAQs, Micron Technology Inc.](https://www.micron.com/sales-support/sales/faqs)
18. [DDR5 DRAM, Micron Technology Inc.](https://www.micron.com/products/memory/dram-components/ddr5-sdram)
19. [Is my RAM compatible with my motherboard, Crucial](https://test.crucial.com/articles/about-memory/is-my-ram-compatible-with-my-motherboard)
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*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Computer hardware › Semiconductor devices & fabrication › Semiconductor memory devices*
*Initially written Sep 17, 2026 · Reviewed: Sep 17, 2026; Sep 30, 2026; Oct 15, 2026 · Edited: Oct 15, 2026 · Last review: Oct 15, 2026*
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