12 articles
Forwarding (CPU pipelining)
Forwarding, also called bypassing, is a pipelined-processor technique that routes an instruction's result directly from a pipeline register to a dependent instruction, resolving most RAW data hazards without stalling.
Hazard (computer architecture)
A hazard, or pipeline hazard, is a condition in a pipelined processor that prevents the next instruction from executing on schedule, resolved by stalls, forwarding, or prediction.
Instruction pipelining
Instruction pipelining, used in pipelined processors, is a design technique that splits instruction execution into stages and overlaps consecutive instructions, raising throughput without lowering each instruction's latency.
Instruction-level parallelism
Instruction-level parallelism (ILP) is the parallelism that exists between instructions of a program written for a serial ISA, exploited by processors through pipelining, superscalar issue, and out-of-order execution.
Memory disambiguation
Memory disambiguation is the problem of determining whether a load and a store refer to the same address, so processors can execute loads speculatively and compilers can reorder memory operations.
Out-of-order execution
Out-of-order execution is a processor technique that runs instructions when their data is ready rather than in program order, first implemented in the IBM System/360 Model 91 in 1967.
Pipeline (computing)
A pipeline, or CPU pipeline, is a processor design dividing instruction execution into stages so several instructions overlap, raising throughput; the classic example has five stages.
Register renaming
Register renaming is a technique in out-of-order processors that rewrites architectural register names onto physical registers, eliminating false dependencies so independent instructions can execute in parallel.
Reorder buffer
The reorder buffer (ROB) is a hardware queue in out-of-order processors that holds instruction results and commits them in program order, providing precise exceptions and simple branch-misprediction recovery.
Speculative execution
Speculative execution is a processor technique that computes instructions before it is certain they are needed, discarding wrong guesses; the same mechanism enables Spectre security attacks.
Superscalar execution
Superscalar execution is a processor technique in which a CPU core issues and executes multiple instructions in the same clock cycle, found at runtime in hardware.
VLIW
VLIW (Very Long Instruction Word) is a processor architecture in which the compiler packs multiple operations into each long instruction word, moving scheduling work out of runtime hardware.