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Chip packaging components and assembly

11 articles

General

Chip on board

Chip on board (COB) is a semiconductor assembly technique in which a bare integrated-circuit die is attached directly to a printed circuit board and connected by wire bonds.

General

Copper wire bonding

Copper wire bonding is a semiconductor packaging technique that connects an integrated circuit die to its lead frame using copper wire, adopted from about 2009 as rising gold prices drove a shift from gold wire.

General

Die attach

Die attach, also called die bonding, is the semiconductor packaging step that bonds a chip die to a lead frame or substrate using epoxy adhesive, solder, or sintered silver.

General

Leadframe

A leadframe is a thin metal structure inside a semiconductor package that carries the chip die, conducts its signals outward, and forms the package pins after molding.

General

Molded underfill

Molded underfill (MUF) is a semiconductor packaging process that combines capillary underfill and overmolding into one epoxy molding step, improving reliability and used in SK hynix HBM since 2019.

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Multi-chip module

A multi-chip module (MCM) is an electronic package that mounts two or more integrated circuit dice on a shared substrate, shortening interconnects and raising circuit density.

General

Package on package

Package on package (PoP) is a semiconductor assembly method in which fully packaged chips, typically a mobile application processor and DRAM, are soldered in a vertical stack.

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Package substrate

A package substrate is the multilayer board inside a semiconductor package that mechanically carries silicon dies and electrically routes their connections to the motherboard, often using Ajinomoto Build-up Film.

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Palomar Technologies

Palomar Technologies is a privately held American manufacturer of automated die attach, wire bonding, and vacuum reflow systems for microelectronic packaging, based in Carlsbad, California, with origins in Hughes Aircraft.

General

Photonic wire bonding

Photonic wire bonding (PWB) is a chip-packaging technique that connects photonic integrated circuits on different chips, fibers, or lasers using 3D polymer waveguides written by direct laser lithography.

General

Underfill

Underfill is a silica-filled epoxy that fills the gap between a flip-chip silicon die and its packaging substrate, redistributing thermomechanical stress to protect solder joints from thermal fatigue.