# High Bandwidth Memory
**High Bandwidth Memory** (HBM) is a type of computer memory in which several DRAM dies are stacked vertically and connected by thousands of through-silicon vias (TSVs) and microbumps, creating an ultra-wide interface that delivers very high data throughput in a small physical footprint.[1](https://www.micron.com/products/memory/hbm) It is standardized by JEDEC, the microelectronics industry standards body, and is the dominant memory technology in AI accelerators and high-performance computing (HPC) systems.[2](https://www.jedec.org/) • [1](https://www.micron.com/products/memory/hbm)
| Key fact | Detail |
|---|---|
| Architecture | Vertically stacked DRAM dies on an optional base die, interconnected by TSVs and microbumps; mounted beside the processor on a 2.5D interposer[1](https://www.micron.com/products/memory/hbm) |
| Interface width | 1024-bit in HBM through HBM3E (HBM, HBM2, and HBM2E use eight 128-bit channels, while HBM3 and HBM3E use sixteen 64-bit channels split into 32 32-bit pseudochannels); doubled to 2048-bit in HBM4, the first widening since 2015[3](https://developer.download.nvidia.com/video/gputechconf/gtc/2019/presentation/s91028-2-pivotal-memory-technologies-enabling-new-generation-of-ai-workloads-presented-by-samsung.pdf) • [4](https://www.tomshardware.com/pc-components/dram/sk-hynix-completes-development-of-hbm4-2-048-bit-interface-and-10-gt-s-speeds-promised) • [26](https://www.synopsys.com/articles/hbm3-ip-dwtb.html) |
| Generations | HBM, HBM2, HBM2E, HBM3, HBM3E, HBM4, in that order of development[5](https://news.skhynix.co.kr/mass-production-hbm-4/) |
| HBM3E bandwidth | Micron: more than 1.2 TB/s per stack; Samsung: up to 1,180 GB/s per stack at 9.2 Gb/s per pin[6](https://www.micron.com/products/memory/hbm/hbm3e) • [7](https://semiconductor.samsung.com/dram/hbm/) |
| HBM4 bandwidth | Micron: greater than 2.8 TB/s per stack at over 11 Gbps; Samsung: up to 3,300 GB/s at 13.0 Gbps; SK hynix: 10 GT/s, 25% above the JEDEC specification[8](https://www.micron.com/products/memory/hbm/hbm4) • [7](https://semiconductor.samsung.com/dram/hbm/) • [4](https://www.tomshardware.com/pc-components/dram/sk-hynix-completes-development-of-hbm4-2-048-bit-interface-and-10-gt-s-speeds-promised) |
| Capacity per stack | HBM3E: 24 GB (8-high) and 36 GB (12-high); HBM4: 36 GB 12-high in volume production, with 48 GB 16-high samples[6](https://www.micron.com/products/memory/hbm/hbm3e) • [8](https://www.micron.com/products/memory/hbm/hbm4) |
| Main producers | SK hynix, Samsung, and Micron[9](https://www.tomshardware.com/pc-components/ram/dram-chip-supply-to-module-makers-could-drop-by-more-than-70-percent-year-on-year-in-2027-says-apacer-ceo-demand-for-hbm-and-server-ram-continues-to-devour-manufacturing-capacity) |
## How it works
A conventional DDR5 module uses a narrow bus driven at high clock speeds. HBM instead uses a highly parallelized, wide-interface architecture: a single HBM3 cube presents a 1024-bit-wide data interface, 16 times wider than a standard DDR5 module, divided into sixteen 64-bit channels, each split into two 32-bit pseudochannels, which lets it move large amounts of data at much lower energy per bit.[1](https://www.micron.com/products/memory/hbm) • [26](https://www.synopsys.com/articles/hbm3-ip-dwtb.html) The stacked dies are connected vertically by TSVs, etched and copper-filled vias that pass through the silicon, and joined by microbumps; the stack sits next to the processor on an interposer, so the connections are short and power consumption per bit is reduced.[1](https://www.micron.com/products/memory/hbm) • [10](https://news.skhynix.com/en/creating-new-values-in-dram-using-through-silicon-via-technology-for-continued-scaling-in-memory-system-performance-and-capacity/)
**Packaging.** HBM is a 2.5D system-in-package: a processor or ASIC is packaged with one or more HBM stacks on a silicon interposer. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging service integrates SoC chips and HBM stacks for HPC products, and its CoWoS-S variant with a silicon interposer has been in volume production for several years.[11](https://investor.tsmc.com/static/annualReports/2025/english/pdf/2025_tsmc_ar_e_ch5.pdf) TSMC has continued enlarging interposer sizes to accommodate more HBMs; in 2025 it certified a 5.5-times-reticle-size interposer for volume production starting in 2026.[12](https://www.cld.tsmc.com/english/dedicatedFoundry/technology/platform_HPC_tech_WLSI) The stacked memory layers consume a substantial portion of the package's power budget, and thermal design is a limiting factor for stacking HBM directly on processors.[13](https://arxiv.org/abs/2101.00969)
## Generations
The generation sequence runs HBM, HBM2, HBM2E, HBM3, HBM3E, and HBM4.[5](https://news.skhynix.co.kr/mass-production-hbm-4/) Samsung launched HBM2 in the first quarter of 2016, built on DDR4 dies with TSVs in 4-high or 8-high stacks, with 1024 I/Os organized as 8 channels of 128 bits and 307 GB/s per stack; the HBM2E update raised throughput by about a third to 410 GB/s and doubled density to 16 GB per stack.[3](https://developer.download.nvidia.com/video/gputechconf/gtc/2019/presentation/s91028-2-pivotal-memory-technologies-enabling-new-generation-of-ai-workloads-presented-by-samsung.pdf)
**HBM3 and HBM3E.** Samsung's HBM3 delivers 6.4 Gb/s per pin and up to 819 GB/s per stack in 16 GB and 24 GB capacities.[7](https://semiconductor.samsung.com/dram/hbm/) HBM3E raised this to 9.2 Gb/s per pin and up to 1,180 GB/s per stack in 24 GB (8-high) and 36 GB (12-high) configurations.[7](https://semiconductor.samsung.com/dram/hbm/) • [6](https://www.micron.com/products/memory/hbm/hbm3e)
**HBM4.** The JEDEC HBM4 standard, released in 2025, doubles the interface to 2048 bits.[8](https://www.micron.com/products/memory/hbm/hbm4) • [4](https://www.tomshardware.com/pc-components/dram/sk-hynix-completes-development-of-hbm4-2-048-bit-interface-and-10-gt-s-speeds-promised) SK hynix announced completion of HBM4 development and mass-production readiness on September 12, 2025, reporting doubled bandwidth and a 40% power-efficiency improvement over the previous generation, and demonstrated a 16-high 48 GB package at CES operating at 10 GT/s, 25% above the JEDEC specification.[14](https://news.skhynix.com/en/sk-hynix-completes-worlds-first-hbm4-development-and-readies-mass-production/) • [15](https://www.tomshardware.com/tech-industry/sk-hynix-shows-16-hi-hbm4-memory-for-ai-accelerators-48-gb-at-10-gt-s-over-a-2-048-interface) Samsung began mass production and commercial shipments of HBM4 built on its 1c (sixth-generation 10-nanometer-class) DRAM with a 4 nm logic base die, reaching up to 13.0 Gbps and 3,300 GB/s per stack in a 36 GB 12-high configuration.[16](https://news.samsung.com/kr/%EC%82%BC%EC%84%B1%EC%A0%84%EC%9E%90-%EC%84%B8%EA%B3%84-%EC%B5%9C%EC%B4%88-%EC%97%85%EA%B3%84-%EC%B5%9C%EA%B3%A0-%EC%84%B1%EB%8A%A5%EC%9D%98-hbm4-%EC%96%91%EC%82%B0-%EC%B6%9C%ED%95%98) • [7](https://semiconductor.samsung.com/dram/hbm/) Micron is in high-volume production of HBM4 36 GB 12-high at over 11 Gb/s pin speeds, exceeding 2.8 TB/s per stack, a 2.3-fold bandwidth increase over its HBM3E with more than 20% better power efficiency, and in 2026 began sampling a 48 GB 16-high version.[8](https://www.micron.com/products/memory/hbm/hbm4)
**HBM4E.** Samsung began shipment of the industry's first HBM4E samples with bandwidth of up to 3.6 TB/s per stack, more than 20% above its HBM4, in a 12-layer 48 GB configuration, with 32 GB (8-layer) and 64 GB (16-layer) variants planned.[17](https://semiconductor.samsung.com/news-events/news/samsung-electronics-begins-shipment-of-industry-first-hbm4e-samples/)
## Why AI workloads use it
[Deep learning](https://www.edgepedia.org/deep-learning) training and inference are frequently memory-bandwidth constrained: if the memory cannot supply data fast enough, the processor idles regardless of its compute throughput.[3](https://developer.download.nvidia.com/video/gputechconf/gtc/2019/presentation/s91028-2-pivotal-memory-technologies-enabling-new-generation-of-ai-workloads-presented-by-samsung.pdf) • [18](https://www.pwc.com/gx/en/industries/technology/pwc-semiconductor-and-beyond-2026-full-report.pdf) HBM's combination of bandwidth, capacity per footprint, and energy per bit makes it the memory of choice for AI accelerators; a single advanced AI accelerator can require several times the DRAM of a standard server.[1](https://www.micron.com/products/memory/hbm) • [19](https://www.techradar.com/pro/the-global-memory-shortage-the-hidden-bottleneck-behind-the-ai-boom)
**Comparison with GDDR.** Graphics DDR (GDDR) memory offers a different trade-off. GDDR7 provides significantly lower bandwidth than HBM3E or HBM4, but consumes less power, costs dramatically less per gigabyte, and does not require expensive advanced packaging such as CoWoS; Nvidia's Rubin CPX inference accelerator uses 128 GB of GDDR7 for long-context inference workloads.[20](https://www.tomshardware.com/pc-components/gpus/nvidias-new-cpx-gpu-aims-to-change-the-game-in-ai-inference-how-the-debut-of-cheaper-and-cooler-gddr7-memory-could-redefine-ai-inference-infrastructure) Research on disaggregated LLM serving similarly pairs GDDR-based accelerators for prefill with HBM-based GPUs for decode to lower cost.[21](https://arxiv.org/abs/2606.29986)
## Supply and market
HBM has been supply-constrained. SK hynix and Micron shifted capacity from DDR5 and LPDDR5 processes to HBM, yet capacity remained fully booked through 2025, and HBM production has reduced capacity available for other DRAM products.[22](https://www.compal.com/mediafiles/sh-meeting/materials/2025/2024_Annual_Report-20250509.pdf) The analyst firm SemiAnalysis estimated that memory would account for roughly 30% of total hyperscaler capital expenditure in calendar 2026, up from about 8% in 2023 and 2024, and that HBM would remain undersupplied through 2027.[23](https://www.tomshardware.com/tech-industry/memory-will-consume-30-percent-of-hyperscaler-spending-this-year) Because HBM and advanced server memory carry higher margins, Samsung, SK hynix, and Micron prioritize them as AI infrastructure spending consumes an increasing share of manufacturing capacity; the CEO of the module maker Apacer said in July 2026 that DRAM chip supply to independent module makers could fall to about 30% of 2026 levels in 2027.[9](https://www.tomshardware.com/pc-components/ram/dram-chip-supply-to-module-makers-could-drop-by-more-than-70-percent-year-on-year-in-2027-says-apacer-ceo-demand-for-hbm-and-server-ram-continues-to-devour-manufacturing-capacity)
Supply security has also shaped chipmaker relationships. Samsung has been the primary HBM3E supplier for AMD's Instinct MI350 accelerators, and in March 2026 AMD and Samsung signed a memorandum of understanding covering HBM4 supply for AMD's upcoming Instinct MI455X accelerator, with Samsung reportedly seeking to extend the relationship into foundry orders.[24](https://www.tomshardware.com/tech-industry/semiconductors/amd-and-samsung-ink-memory-supply-memorandum-for-epyc-and-instinct-products-unprecedented-deal-also-includes-scope-for-foundry-partnership) • [25](https://www.tomshardware.com/tech-industry/semiconductors/amd-seeks-broader-partnership-with-samsung-as-it-looks-to-secure-memory-supply-samsung-reportedly-hopes-to-turn-its-memory-supply-relationship-with-amd-into-foundry-orders-for-logic-chips)
## References
1. [High-bandwidth memory (HBM), Micron Technology](https://www.micron.com/products/memory/hbm)
2. [JEDEC](https://www.jedec.org/)
3. [Pivotal Memory Technologies Enabling a New Generation of AI Workloads, Samsung at GTC 2019](https://developer.download.nvidia.com/video/gputechconf/gtc/2019/presentation/s91028-2-pivotal-memory-technologies-enabling-new-generation-of-ai-workloads-presented-by-samsung.pdf)
4. [SK hynix completes development of next-gen HBM4, Tom's Hardware](https://www.tomshardware.com/pc-components/dram/sk-hynix-completes-development-of-hbm4-2-048-bit-interface-and-10-gt-s-speeds-promised)
5. [SK하이닉스, 세계 최초 'HBM4' 개발 완료하고 양산 체제 구축, SK hynix Newsroom](https://news.skhynix.co.kr/mass-production-hbm-4/)
6. [HBM3E, Micron Technology](https://www.micron.com/products/memory/hbm/hbm3e)
7. [HBM, Samsung Semiconductor Global](https://semiconductor.samsung.com/dram/hbm/)
8. [HBM4, Micron Technology](https://www.micron.com/products/memory/hbm/hbm4)
9. [DRAM chip supply to module makers could drop by more than 70% year-on-year in 2027, says Apacer CEO, Tom's Hardware](https://www.tomshardware.com/pc-components/ram/dram-chip-supply-to-module-makers-could-drop-by-more-than-70-percent-year-on-year-in-2027-says-apacer-ceo-demand-for-hbm-and-server-ram-continues-to-devour-manufacturing-capacity)
10. [Creating New Values in DRAM Using Through-Silicon-Via Technology, SK hynix Newsroom](https://news.skhynix.com/en/creating-new-values-in-dram-using-through-silicon-via-technology-for-continued-scaling-in-memory-system-performance-and-capacity/)
11. [TSMC 3DFabric, 2025 Annual Report chapter 5](https://investor.tsmc.com/static/annualReports/2025/english/pdf/2025_tsmc_ar_e_ch5.pdf)
12. [HPC Platform, TSMC 3DFabric](https://www.cld.tsmc.com/english/dedicatedFoundry/technology/platform_HPC_tech_WLSI)
13. [Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling, arXiv](https://arxiv.org/abs/2101.00969)
14. [SK hynix Completes World's First HBM4 Development and Readies Mass Production, SK hynix Newsroom](https://news.skhynix.com/en/sk-hynix-completes-worlds-first-hbm4-development-and-readies-mass-production/)
15. [SK hynix shows 16-Hi HBM4 memory for AI accelerators, Tom's Hardware](https://www.tomshardware.com/tech-industry/sk-hynix-shows-16-hi-hbm4-memory-for-ai-accelerators-48-gb-at-10-gt-s-over-a-2-048-interface)
16. [삼성전자, 세계 최초 업계 최고 성능의 HBM4 양산 출하, Samsung Newsroom Korea](https://news.samsung.com/kr/%EC%82%BC%EC%84%B1%EC%A0%84%EC%9E%90-%EC%84%B8%EA%B3%84-%EC%B5%9C%EC%B4%88-%EC%97%85%EA%B3%84-%EC%B5%9C%EA%B3%A0-%EC%84%B1%EB%8A%A5%EC%9D%98-hbm4-%EC%96%91%EC%82%B0-%EC%B6%9C%ED%95%98)
17. [Samsung Electronics Begins Shipment of Industry-First HBM4E Samples, Samsung Semiconductor Global](https://semiconductor.samsung.com/news-events/news/samsung-electronics-begins-shipment-of-industry-first-hbm4e-samples/)
18. [Semiconductor and Beyond 2026, PwC](https://www.pwc.com/gx/en/industries/technology/pwc-semiconductor-and-beyond-2026-full-report.pdf)
19. [The global memory shortage: The hidden bottleneck behind the AI boom, TechRadar Pro](https://www.techradar.com/pro/the-global-memory-shortage-the-hidden-bottleneck-behind-the-ai-boom)
20. [Nvidia's new CPX GPU aims to change the game in AI inference, Tom's Hardware](https://www.tomshardware.com/pc-components/gpus/nvidias-new-cpx-gpu-aims-to-change-the-game-in-ai-inference-how-the-debut-of-cheaper-and-cooler-gddr7-memory-could-redefine-ai-inference-infrastructure)
21. [HBM Is Not All You Need: Efficient Disaggregated LLM Serving across Memory-heterogeneous Accelerators, arXiv](https://arxiv.org/abs/2606.29986)
22. [Compal 2024 Annual Report](https://www.compal.com/mediafiles/sh-meeting/materials/2025/2024_Annual_Report-20250509.pdf)
23. [Memory will consume 30% of hyperscaler AI data center spending this year, Tom's Hardware](https://www.tomshardware.com/tech-industry/memory-will-consume-30-percent-of-hyperscaler-spending-this-year)
24. [AMD and Samsung ink memory supply memorandum for EPYC and Instinct products, Tom's Hardware](https://www.tomshardware.com/tech-industry/semiconductors/amd-and-samsung-ink-memory-supply-memorandum-for-epyc-and-instinct-products-unprecedented-deal-also-includes-scope-for-foundry-partnership)
25. [AMD seeks 'broader partnership' with Samsung as it looks to secure memory supply, Tom's Hardware](https://www.tomshardware.com/tech-industry/semiconductors/amd-seeks-broader-partnership-with-samsung-as-it-looks-to-secure-memory-supply-samsung-reportedly-hopes-to-turn-its-memory-supply-relationship-with-amd-into-foundry-orders-for-logic-chips)
26. [What Designers Need to Know About HBM3, Synopsys IP](https://www.synopsys.com/articles/hbm3-ip-dwtb.html)
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*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Computer hardware › Graphics & GPU hardware › GPGPU & GPU computing › GPU memory and host interconnect*
*Initially written Sep 17, 2026 · Reviewed: Sep 30, 2026; Oct 15, 2026 · Edited: Sep 30, 2026; Oct 11, 2026; Oct 15, 2026 · Last review: Oct 15, 2026*
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