# NOR gate

A NOR gate is a digital logic gate whose output is high (1) only when every one of its inputs is low (0); it performs the complement of the OR operation, which is why its name abbreviates NOT OR. For two inputs the Boolean expression is \( Y = \overline{A + B} \), and the gate's symbol is an OR shape with a bubble (inversion circle) on the output.<sup>[1](https://faculty.kfupm.edu.sa/coe/aimane/coe202/Univ_Gates.pdf)</sup>

| Key fact | Detail |
|---|---|
| Boolean function | \( Y = \overline{A + B} \) for two inputs; output 1 only for inputs 0, 0<sup>[1](https://faculty.kfupm.edu.sa/coe/aimane/coe202/Univ_Gates.pdf)</sup> |
| Truth table | 00 → 1; 01 → 0; 10 → 0; 11 → 0<sup>[1](https://faculty.kfupm.edu.sa/coe/aimane/coe202/Univ_Gates.pdf)</sup> |
| Universality | NOR is a universal gate: NOT, OR, AND, and any other Boolean function can be built from NOR gates alone<sup>[2](https://archive.nptel.ac.in/content/storage2/courses/122104013/node27.html)</sup> |
| CMOS construction | Two pMOS transistors in series form the pull-up path; two nMOS transistors in parallel form the pull-down path<sup>[3](https://archive.nptel.ac.in/content/storage2/courses/117103066/chap1/slides/slide8.htm)</sup> |
| Classic application | Two cross-coupled NOR gates form the SR latch, a one-bit storage circuit; the input combination S = R = 1 is forbidden<sup>[4](https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/latch_and_flip_flop.html)</sup> |
| Standard IC | The SN74HC02 contains four independent 2-input NOR gates, operates from 2 V to 6 V, and has a typical propagation delay of 9 ns at 4.5 V<sup>[5](https://www.ti.com/lit/gpn/SN74HC02)</sup> |

## Truth table and behavior

The NOR operation is the complement of OR: where an [OR gate](https://www.edgepedia.org/or-gate) outputs 1 when either input is 1, the NOR gate outputs 0 in exactly those cases and 1 only when both inputs are 0.<sup>[1](https://faculty.kfupm.edu.sa/coe/aimane/coe202/Univ_Gates.pdf)</sup> In words, the output is high only when neither input is high, so any nonzero input takes the output low.<sup>[6](https://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/nor.html)</sup> Gates with three or more inputs follow the same rule: a multi-input NOR is a multi-input OR followed by a NOT.<sup>[7](https://www.cs.emory.edu/~cheung/Courses/355/Syllabus/1-circuits/elem-dig.html)</sup>

## A universal gate

A universal gate is a gate from which any [Boolean function](https://www.edgepedia.org/boolean-function) can be implemented without any other gate type. NAND and NOR are the two universal gates, and this is practically important because they are economical and easy to fabricate; they are the basic gates used in integrated-circuit digital logic families.<sup>[1](https://faculty.kfupm.edu.sa/coe/aimane/coe202/Univ_Gates.pdf)</sup> The universality follows from [De Morgan's laws](https://www.edgepedia.org/de-morgans-laws), since \( \overline{A + B} = \overline{A} \cdot \overline{B} \):<sup>[8](https://cs.longwood.edu/courses/cmsc121/resources/s24/functional-equivalence/)</sup>

- **NOT**: tie both inputs of a NOR together, giving \( \overline{A + A} = \overline{A} \).<sup>[9](https://myslu.stlawu.edu/~ehar/Spring12/220/appendix_c_2.html)</sup>
- **OR**: follow a NOR with a NOR wired as an inverter, since \( A + B = \overline{\overline{A + B}} \).<sup>[9](https://myslu.stlawu.edu/~ehar/Spring12/220/appendix_c_2.html)</sup>
- **AND**: invert each input with its own NOR, then feed both into a third NOR, since \( A \cdot B = \overline{\overline{A} + \overline{B}} \); three NOR gates in total.<sup>[9](https://myslu.stlawu.edu/~ehar/Spring12/220/appendix_c_2.html)</sup>
- **NAND**: an AND built from NORs followed by a NOR inverter, four gates in total.<sup>[10](https://www.jmc.edu/econtent/ug/4602_Computer%20Organization%20and%20Architecture.pdf)</sup>

Because NOT, AND, and OR together suffice to build any logic circuit, NOR alone can build any circuit whatsoever.<sup>[11](https://www.cs.cornell.edu/courses/cs3410/2025sp/notes/logic.html)</sup> The idea of such single-operator completeness predates hardware: it goes back to the late 1800s in the work of the logician and philosopher Charles Sanders Peirce, who developed the foundations of these constructions long before transistors existed.<sup>[12](https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/logic_gates.html)</sup> By contrast, the non-inverting gates AND and OR cannot produce an inversion and so lack this versatility.<sup>[6](https://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/nor.html)</sup>

## CMOS implementation

In CMOS technology a two-input NOR gate uses a pull-up sub-circuit of two pMOS transistors in series and a pull-down path of two nMOS transistors in parallel. The series pMOS pair conducts a logic 1 to the output only when both inputs are at logic 0; if either input is at logic 1, one of the parallel nMOS transistors conducts and pulls the output to logic 0.<sup>[3](https://archive.nptel.ac.in/content/storage2/courses/117103066/chap1/slides/slide8.htm)</sup> This transistor arrangement is the mirror image of the [NAND gate](https://www.edgepedia.org/nand-gate), which places its pMOS transistors in parallel and its nMOS transistors in series.<sup>[13](https://www.egr.msu.edu/classes/ece410/salem/files/s16/lectures/Ch2_S2_N.pdf)</sup>

## The SR latch

The most familiar sequential application of the NOR gate is the SR (set-reset) latch, built from two cross-coupled NOR gates in which each gate's output feeds the other's input. The circuit is bistable: with S = R = 0 it holds whichever of its two stable states, Q = 1 or Q = 0, it last reached, so it stores one bit. A pulse on S forces Q = 1 (set), a pulse on R forces Q = 0 (reset), and the combination S = R = 1 is a forbidden state, sometimes called a restricted combination, because both NOR gates then output 0 and the logical equation Q = Q breaks down.<sup>[4](https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/latch_and_flip_flop.html)</sup><sup> • </sup><sup>[14](https://de-iitr.vlabs.ac.in/exp/nor-gate-latch/theory.html)</sup> Upstream circuitry, as in the D latch, prevents that prohibited input from ever reaching the latch.<sup>[4](https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/latch_and_flip_flop.html)</sup>

## Integrated circuits

NOR gates have long been supplied as standard catalog parts. The 7402 quad 2-input NOR gate is the TTL-family counterpart of the 7400 quad NAND.<sup>[6](https://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/nor.html)</sup> In the CMOS HC family, the SN74HC02 contains four independent 2-input NOR gates, each performing \( Y = \overline{A + B} \) in positive logic, with a supply range of 2 V to 6 V, push-pull outputs rated at 5.2 mA, and a typical propagation delay of 9 ns at 4.5 V (23 ns maximum).<sup>[5](https://www.ti.com/lit/gpn/SN74HC02)</sup> [Texas Instruments](https://www.edgepedia.org/texas-instruments)' own application example for this part is an active-low SR latch used as a tamper indicator: when a tamper switch outputs low, the latch output Q goes high and stays high until the system controller sends a low signal to the R input.<sup>[5](https://www.ti.com/lit/gpn/SN74HC02)</sup>

## References

1. [Universal Gates: NAND and NOR, KFUPM COE 202 course notes](https://faculty.kfupm.edu.sa/coe/aimane/coe202/Univ_Gates.pdf)
2. [Universality of certain gates, NPTEL Digital Circuits](https://archive.nptel.ac.in/content/storage2/courses/122104013/node27.html)
3. [CMOS Circuits: A Brief Introduction, NPTEL (Figure 1.6, two-input CMOS NOR gate)](https://archive.nptel.ac.in/content/storage2/courses/117103066/chap1/slides/slide8.htm)
4. [Latch and flip flop, Clayton Cafiero, University of Vermont](https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/latch_and_flip_flop.html)
5. [SNx4HC02 Quadruple 2-Input Positive-NOR Gates datasheet (Rev. G), Texas Instruments](https://www.ti.com/lit/gpn/SN74HC02)
6. [NOR Gate, HyperPhysics, Georgia State University](https://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/nor.html)
7. [Elementary digital circuits, Emory CS 355 course notes](https://www.cs.emory.edu/~cheung/Courses/355/Syllabus/1-circuits/elem-dig.html)
8. [Functional equivalence in circuits, CMSC 121, Longwood University](https://cs.longwood.edu/courses/cmsc121/resources/s24/functional-equivalence/)
9. [CS 220 Appendix C Logic Design Solutions, St. Lawrence University](https://myslu.stlawu.edu/~ehar/Spring12/220/appendix_c_2.html)
10. [NOR as a Universal Gate, JMC Computer Organization and Architecture e-content](https://www.jmc.edu/econtent/ug/4602_Computer%20Organization%20and%20Architecture.pdf)
11. [Gates & Logic, CS 3410, Cornell University](https://www.cs.cornell.edu/courses/cs3410/2025sp/notes/logic.html)
12. [Logic gates, Clayton Cafiero, University of Vermont](https://www.uvm.edu/~cbcafier/cs2210/content/04_logic_gates/logic_gates.html)
13. [CMOS NOR Gate lecture notes, ECE 410, Michigan State University](https://www.egr.msu.edu/classes/ece410/salem/files/s16/lectures/Ch2_S2_N.pdf)
14. [NOR gate latch theory, Virtual Labs, IIT Roorkee](https://de-iitr.vlabs.ac.in/exp/nor-gate-latch/theory.html)

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*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Computer hardware › Semiconductor devices & fabrication › Integrated circuits and chip families*

*Initially written Sep 17, 2026 · Reviewed: Oct 15, 2026 · Edited: Oct 15, 2026 · Last review: Oct 15, 2026*

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