# RISC-V

**RISC-V** (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established [reduced instruction set computer](https://www.edgepedia.org/reduced-instruction-set-computer) (RISC) principles.<sup>[1](https://docs.riscv.org/)</sup> The ISA consists of a base integer ISA that every implementation is required to include, together with optional extensions built on that base, and [RISC-V International](https://www.edgepedia.org/risc-v-international), a global non-profit standards body, develops, ratifies, and maintains it.<sup>[2](https://riscv.github.io/riscv-isa-manual/snapshot/spec/index.html)</sup><sup> • </sup><sup>[3](https://riscv.org/about/faq/)</sup> The ISA and its ratified extensions are royalty free under open licenses, so anyone may build open-source or proprietary processors, software, and services on them without paying a fee for the instruction set itself.<sup>[4](https://riscv.org/about/)</sup>

| Key fact | Detail |
|---|---|
| Type | Open standard ISA based on RISC principles; royalty free and open under permanently open licenses<sup>[1](https://docs.riscv.org/)</sup><sup> • </sup><sup>[4](https://riscv.org/about/)</sup> |
| Origin | Started May 2010 at UC Berkeley's Par Lab by Prof. Krste Asanović and graduate students Yunsup Lee and Andrew Waterman; first manual published May 13, 2011<sup>[4](https://riscv.org/about/)</sup> |
| Structure | Base integer ISA (RV32I, RV32E, RV64I, RV64E, or RV128I) plus optional letter-named extensions such as M, A, F, D, C, and V<sup>[2](https://riscv.github.io/riscv-isa-manual/snapshot/spec/index.html)</sup> |
| Governance | RISC-V Foundation founded 2015 with 36 founding members; incorporated in Switzerland since March 2020 as RISC-V International<sup>[4](https://riscv.org/about/)</sup><sup> • </sup><sup>[3](https://riscv.org/about/faq/)</sup> |
| Application baseline | RVA23 profile, ratified October 21, 2024, makes the Vector and Hypervisor extensions mandatory for 64-bit application processors<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> |
| Software support | Linux kernel, GCC, LLVM, and Debian 13 (the first official Debian riscv64 release) support the architecture<sup>[6](https://www.debian.org/releases/trixie/riscv64/ch02s01.en.html)</sup> |
| Adoption forecast | RISC-V processors projected to account for almost a quarter of the global market by 2030 (Omdia research)<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> |

## Design: a base ISA plus modular extensions

The defining design decision is modularity. A RISC-V ISA consists of a base integer ISA together with optional extensions; the base is intentionally kept small, containing only the instructions needed to give compilers, assemblers, linkers, and operating systems an adequate target, and it serves as a framework upon which more customized processor ISAs may be constructed.<sup>[2](https://riscv.github.io/riscv-isa-manual/snapshot/spec/index.html)</sup> An ISA string opens with one of the base variants RV32I, RV32E, RV64I, RV64E, or RV128I, whose names show how many bits of address space the base integer ISA supports; additional standard extensions are assigned reserved letters, for example "Q" designating quad-precision floating point and "C" the 16-bit compressed instruction format.<sup>[7](https://docs.riscv.org/reference/isa/unpriv/rv32.html)</sup> The compressed format was built into the encoding scheme from the start rather than added later, but it is not mandatory, and the base RV32I ISA uses less than 1/8 of the encoding space in the 32-bit instruction word.<sup>[8](https://riscv.github.io/riscv-isa-manual/snapshot/spec/)</sup>

Modularity is also the mechanism for evolution: new instructions are added as optional extensions instead of releasing new versions of the whole ISA, which lets one specification cover a large spectrum of applications and increases software reuse.<sup>[9](https://doi.org/10.2514/1.I010735)</sup> The standard defines a "general" subset (G), comprising the IMAFD extensions, as the set required for general-purpose computing systems.<sup>[9](https://doi.org/10.2514/1.I010735)</sup>

## Profiles

Because implementations may pick different extension combinations, RISC-V International defines profiles that specify which ISA features are mandatory or optional, giving software developers a common target.<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> Mandatory extensions can be assumed present, while optional extensions can be discovered at runtime and leveraged by optimized middleware, libraries, and applications.<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> A major release of an application profile provides forward binary compatibility for software that ran on the previous major release of the same profile family.<sup>[10](https://riscv.atlassian.net/wiki/spaces/WPMU/pages/462258208/RISC-V%2BProfile%2BPolicy)</sup>

**RVA23** is the central profile for application processors. Ratified on October 21, 2024, it aligns implementations of RISC-V 64-bit application processors that run rich operating system stacks from standard binary OS distributions.<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> Its two headline mandatory components are the Vector extension, which accelerates math-intensive workloads including AI/ML, cryptography, and compression, and the [Hypervisor](https://www.edgepedia.org/hypervisor) extension, which enables virtualization for enterprise workloads.<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> The profile is the baseline requirement for the Android RISC-V ABI.<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> For servers, the ratified Server SoC specification requires that application processor harts (individual hardware CPU cores in RISC-V) support the RVA23S64 ISA profile.<sup>[11](https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc)</sup> A microcontroller profile (RVM) was in draft in 2025 with ratification expected in 2026.<sup>[12](https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf)</sup>

## Vector extension

It adds 32 vector registers and seven unprivileged CSRs (vstart, vxsat, vxrm, vcsr, vtype, vl, and vlenb) to a base scalar RISC-V ISA, and is intended to provide general support for data-parallel execution within the 32-bit instruction encoding space.<sup>[13](https://docs.riscv.org/reference/isa/unpriv/v-st-ext)</sup>

Unlike fixed-width SIMD designs, RVV uses a vector-length-agnostic programming model: each hart defines two implementation parameters, ELEN (the maximum element size in bits, at least 8 and a power of 2) and VLEN (the number of bits in a single vector register, a power of 2 no greater than 2<sup>16</sup>), and the same code runs on machines with different register lengths.<sup>[13](https://docs.riscv.org/reference/isa/unpriv/v-st-ext)</sup> Smaller extensions for embedded use carry a "Zve" prefix, while the larger single-letter V extension for application processors requires a minimum VLEN of 128 bits; "Zvl" extensions raise the minimum vector length further.<sup>[14](https://docs.riscv.org/reference/isa/extensions/vector/_attachments/riscv-v-spec.pdf)</sup> A vector cryptography specification (Zvkned, Zvknh[ab], Zvkg, Zvksed, Zvksh, and related extensions) builds on the vector registers and requires data-independent execution latency for the cryptography-specific instructions.<sup>[15](https://docs.riscv.org/reference/isa/unpriv/vector-crypto.html)</sup>

## Privileged architecture and security

The privileged specification defines standard privilege levels: machine mode (M-Mode), supervisor mode (S-Mode), and user mode (U-Mode), which separate more privileged software from less privileged software.<sup>[16](https://github.com/riscv/riscv-security-model/blob/main/specification/src/chapter3.adoc)</sup> The Hypervisor extension extends S-Mode into hypervisor-extended supervisor mode (HS-Mode) and a virtual supervisor mode (VS-Mode) for guests, and extends U-Mode into virtual user mode (VU-Mode); isolation of guests is enforced using two-stage address translation and protection.<sup>[16](https://github.com/riscv/riscv-security-model/blob/main/specification/src/chapter3.adoc)</sup> Physical memory access is governed by PMP/Smepmp mechanisms and by physical memory attributes (PMA), which capture inherent hardware properties such as read-only ROM regions and non-cacheable device regions and are checked on every physical access by a PMA checker.<sup>[16](https://github.com/riscv/riscv-security-model/blob/main/specification/src/chapter3.adoc)</sup>

[Control-flow integrity](https://www.edgepedia.org/control-flow-integrity) is addressed by two unprivileged extensions: Zicfilp provides landing pads for forward-edge CFI, and Zicfiss provides a shadow stack for backward-edge CFI, building on the ISA's conventions for calls, returns, and indirect jumps.<sup>[17](https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/cfi.adoc)</sup> A formal executable model of the ISA is maintained in the Sail RISC-V project.<sup>[18](https://github.com/riscv/sail-riscv)</sup>

## History and governance

The instruction set was started in May 2010 as part of the Parallel Computing Laboratory (Par Lab) at UC Berkeley, directed by Prof. [David Patterson](https://www.edgepedia.org/david-patterson-computer-scientist), with Prof. Krste Asanović and graduate students Yunsup Lee and Andrew Waterman as the originators.<sup>[4](https://riscv.org/about/)</sup> The name honors the prior Berkeley RISC projects (RISC-I, RISC-II, and so on), with "V" being the Roman numeral five for the fifth such effort.<sup>[3](https://riscv.org/about/faq/)</sup> The first publication describing the instruction set was the Par Lab report *The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA* (EECS-2011-62), by Waterman, Lee, Patterson, and Asanović, dated May 13, 2011.<sup>[4](https://riscv.org/about/)</sup> The first version of the instruction manual was published in May 2011.<sup>[12](https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf)</sup>

Early milestones followed quickly: the first tapeout of a RISC-V chip, in 28 nm FDSOI process technology donated by ST Microelectronics, in 2011; a 2014 paper arguing the case for free and open instruction sets; the first RISC-V Workshop in January 2015; and the launch of the RISC-V Foundation later that year with 36 founding members.<sup>[4](https://riscv.org/about/)</sup> No patents were filed related to RISC-V in these projects, and the ISA encoding was effectively put into the public domain when the tech reports were published, with the report text later placed under a [Creative Commons license](https://www.edgepedia.org/creative-commons-license).<sup>[4](https://riscv.org/about/)</sup> In March 2020 the RISC-V International Association moved its incorporation to Switzerland, a decision the board said was made to ensure continued ecosystem growth of the open standard.<sup>[3](https://riscv.org/about/faq/)</sup> Today the organization counts more than 4,500 members across 70 countries, and its community has grown to more than 16,000 engineers.<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup> In 2025 it achieved ISO/IEC JTC 1 PAS Submitter status, a step toward formal international standardization.<sup>[12](https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf)</sup>

The specification itself is developed openly. The RISC-V Instruction Set Manual is organized into Volume I (Unprivileged [Architecture](https://www.edgepedia.org/architecture)), Volume II (Privileged Architecture), and Volume III (Profiles), is licensed under Creative Commons Attribution 4.0 International, and is maintained in a public GitHub repository where the issue mechanism accepts input on the specification.<sup>[19](https://github.com/riscv/riscv-isa-manual)</sup><sup> • </sup><sup>[3](https://riscv.org/about/faq/)</sup>

## Software ecosystem

Mainstream software support has matured. GCC and LLVM both implement the RISC-V target, with LLVM aiming to track the most recent ratified versions of the base ISAs and extensions.<sup>[20](https://llvm.org/docs/RISCVUsage.html)</sup> The Linux kernel documents RISC-V boot requirements, including UEFI boot via the RISCV_EFI_BOOT_PROTOCOL.<sup>[21](https://www.kernel.org/doc/html/latest/arch/riscv/boot.html)</sup> Debian GNU/Linux 13 ships the first official release of Debian for the 64-bit little-endian RISC-V architecture (riscv64), and since July 2023 the Debian repository has been the official package repository for that port.<sup>[6](https://www.debian.org/releases/trixie/riscv64/ch02s01.en.html)</sup><sup> • </sup><sup>[22](https://wiki.debian.org/RISC-V/)</sup>

## Industry adoption

Adoption has spread across several verticals. In March 2025 [Infineon Technologies](https://www.edgepedia.org/infineon-technologies), the global market leader in automotive microcontrollers with a 28.5 percent market share (TechInsights, 2001 through 2023), announced it would launch a new automotive microcontroller family based on RISC-V within its [AURIX](https://www.edgepedia.org/infineon-aurix) brand, becoming the first semiconductor supplier to announce an automotive RISC-V MCU family.<sup>[23](https://www.infineon.com/press-release/2025/infatv202503-067)</sup> In data center and HPC, the Server SoC and Boot requirements specifications were ratified, the RISC-V Server Platform specification is expected to be officially ratified by the end of 2026, and ACPI 6.6, published by UEFI in May 2025, includes native RISC-V support for the first time.<sup>[12](https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf)</sup> The first RISC-V-based cloud instances were introduced in 2025 by Scaleway.<sup>[12](https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf)</sup>

**AI and HPC momentum** accelerated in 2025. NVIDIA announced at the 2025 RISC-V Summit in China that its CUDA software platform will be made compatible with RISC-V on the CPU side, allowing RISC-V to serve as the main processor for CUDA-based systems, a role traditionally filled by x86 or Arm cores.<sup>[24](https://www.tomshardware.com/pc-components/gpus/nvidias-cuda-platform-now-supports-risc-v-support-brings-open-source-instruction-set-to-ai-platforms-joining-x86-and-arm)</sup> In Europe, EuroHPC JU formally launched DARE in March 2025, a RISC-V-centric HPC/AI initiative coordinated by the [Barcelona Supercomputing Center](https://www.edgepedia.org/barcelona-supercomputing-center) with €120M of EU funding plus national co-funding, under a six-year framework partnership running to 2030.<sup>[12](https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf)</sup> Omdia research projects that RISC-V processors will account for almost a quarter of the global market by 2030.<sup>[5](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)</sup>

## References

1. [RISC-V Ratified Specifications Library, RISC-V International](https://docs.riscv.org/)
2. [The RISC-V Instruction Set Manual (snapshot), riscv-isa-manual](https://riscv.github.io/riscv-isa-manual/snapshot/spec/index.html)
3. [FAQ, RISC-V International](https://riscv.org/about/faq/)
4. [About RISC-V, RISC-V International](https://riscv.org/about/)
5. [RISC-V Announces Ratification of the RVA23 Profile Standard, RISC-V International (October 21, 2024)](https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/)
6. [Debian GNU/Linux 13 Installation Guide, Supported Hardware (riscv64)](https://www.debian.org/releases/trixie/riscv64/ch02s01.en.html)
7. [RISC-V ISA: RV32 and RV64 base chapters, docs.riscv.org](https://docs.riscv.org/reference/isa/unpriv/rv32.html)
8. [The RISC-V Instruction Set Manual (snapshot), riscv.github.io](https://riscv.github.io/riscv-isa-manual/snapshot/spec/)
9. [Leveraging the Openness and Modularity of RISC-V in Space, Journal of Aerospace Information Systems](https://doi.org/10.2514/1.I010735)
10. [RISC-V Profile Policy, RISC-V Tech Hub](https://riscv.atlassian.net/wiki/spaces/WPMU/pages/462258208/RISC-V%2BProfile%2BPolicy)
11. [RISC-V Server Platform requirements, riscv-non-isa GitHub](https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc)
12. [RISC-V Annual Report 2025, RISC-V International](https://riscv.org/wp-content/uploads/2026/01/RISC-V-Annual-Report-2025.pdf)
13. ["V" Standard Extension for Vector Operations, Version 1.0, docs.riscv.org](https://docs.riscv.org/reference/isa/unpriv/v-st-ext)
14. [Standard Vector Extensions (riscv-v-spec), docs.riscv.org](https://docs.riscv.org/reference/isa/extensions/vector/_attachments/riscv-v-spec.pdf)
15. [Cryptography Extensions: Vector Instructions, Version 1.0, docs.riscv.org](https://docs.riscv.org/reference/isa/unpriv/vector-crypto.html)
16. [RISC-V security building blocks, riscv-security-model specification](https://github.com/riscv/riscv-security-model/blob/main/specification/src/chapter3.adoc)
17. [Control-flow integrity extensions (Zicfilp, Zicfiss), riscv-isa-manual](https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/cfi.adoc)
18. [Sail RISC-V model, GitHub](https://github.com/riscv/sail-riscv)
19. [riscv-isa-manual repository, GitHub](https://github.com/riscv/riscv-isa-manual)
20. [User Guide for RISC-V Target, LLVM](https://llvm.org/docs/RISCVUsage.html)
21. [RISC-V Kernel Boot Requirements, The Linux Kernel documentation](https://www.kernel.org/doc/html/latest/arch/riscv/boot.html)
22. [RISC-V, Debian Wiki](https://wiki.debian.org/RISC-V/)
23. [Infineon brings RISC-V to the automotive industry, Infineon press release (March 6, 2025)](https://www.infineon.com/press-release/2025/infatv202503-067)
24. [Nvidia's CUDA platform now supports RISC-V, Tom's Hardware (July 2025)](https://www.tomshardware.com/pc-components/gpus/nvidias-cuda-platform-now-supports-risc-v-support-brings-open-source-instruction-set-to-ai-platforms-joining-x86-and-arm)

---
*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Computer hardware › Embedded & soft processors › Soft processors & open hardware › RISC-V*

*Initially written Sep 17, 2026 · Reviewed: Sep 17, 2026; Sep 30, 2026; Oct 15, 2026 · Edited: Oct 15, 2026 · Last review: Oct 15, 2026*

*Copyright 2026 EdgeChat AI, a subsidiary of Biostate AI.*

License: Edgepedia Community License 1.0, https://www.edgepedia.org/edgepedia/license