# SSE2

**SSE2** ([Streaming SIMD Extensions](https://www.edgepedia.org/streaming-simd-extensions) 2) is an x86 instruction set extension introduced by Intel in the [Pentium 4](https://www.edgepedia.org/pentium-4) and Intel Xeon processors. It consists of a set of instructions that operate on the XMM and MXCSR registers and perform single instruction, multiple data (SIMD) operations on double-precision floating-point values and on integer values, with several instructions also operating in the MMX registers.<sup>[1](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366821.pdf)</sup> Intel's announcement of the NetBurst micro-architecture described SSE2 as adding 144 new instructions, including 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point instructions.<sup>[2](https://www.intel.com/pressroom/archive/releases/2000/dp082200.htm)</sup>

| Key fact | Detail |
|---|---|
| Introduced with | Pentium 4 and Intel Xeon processors (IA-32 architecture)<sup>[1](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366821.pdf)</sup> |
| Instruction count | 144 new instructions, including 128-bit SIMD integer and 128-bit SIMD double-precision floating-point arithmetic<sup>[2](https://www.intel.com/pressroom/archive/releases/2000/dp082200.htm)</sup> |
| Registers used | XMM registers and the MXCSR control/status register; several instructions also operate in MMX registers<sup>[1](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366821.pdf)</sup> |
| Data types added | Packed double-precision floating-point values and 128-bit packed integers<sup>[3](https://www.intel.com/content/www/us/en/support/articles/000005779/processors.html)</sup> |
| CPUID detection | CPUID.01H:EDX.SSE2[bit 26]<sup>[4](https://www.intel.com/content/www/us/en/developer/articles/technical/trusted-cpu-feature-detection-library-for-intel-software-guard-extensions-intel-sgx.html)</sup> |
| Notable instructions | CLFLUSH (cache-line flush), MOVQ2DQ, MOVDQ2Q, MOVNTI, and the XMM variant of MOVD<sup>[5](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366521.pdf)</sup><sup> • </sup><sup>[6](https://docs.amd.com/api/khub/documents/j44LvPXzuuXgM0WyHKQfeQ/content)</sup> |
| Baseline status | Included in the x64 instruction set; required for installing 64-bit Windows 10<sup>[7](https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-instructions)</sup><sup> • </sup><sup>[8](https://learn.microsoft.com/en-ie/answers/questions/bb1b471b-4575-4a52-ae91-10f124b69795/win-10-update?forum=windows-all)</sup> |

## Position in the SIMD lineage

Intel's IA-32 SIMD support progressed in stages. MMX technology introduced SIMD capability with 64-bit MMX registers and 64-bit packed integer data types. The original Streaming SIMD Extensions (SSE), introduced in the [Pentium III](https://www.edgepedia.org/pentium-iii) processor family, expanded this model with packed and scalar single-precision floating-point values held in 128-bit registers. SSE2 extends the same execution model with support for packed double-precision floating-point values and for 128-bit packed integers.<sup>[3](https://www.intel.com/content/www/us/en/support/articles/000005779/processors.html)</sup> AMD's architecture manuals classify SSE2 among the *legacy* SSE subsets, together with SSE1, SSE3, SSSE3, SSE4.1, SSE4.2, and SSE4A, all of which support 128-bit vector operands; the *extended* subsets (AVX, AVX2, AVX512, and others) add wider operands and three- or four-operand forms.<sup>[9](https://docs.amd.com/api/khub/documents/sfvvekC9mDflu6vd3R0NXA/content)</sup>

## What the instructions do

SSE2 instructions perform SIMD operations on double-precision floating-point values and on integer values in the XMM and MXCSR registers.<sup>[1](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366821.pdf)</sup> The integer side is a widening of the earlier sets: all of the 64-bit SIMD integer instructions introduced with MMX technology and the SSE extensions, with the exception of PSHUFW, were extended by SSE2 to operate on 128-bit packed integer operands located in XMM registers. The 128-bit versions follow the same packed-operand conventions as the 64-bit versions; where the 64-bit PADDB operates on 8 packed bytes, the 128-bit version operates on 16 packed bytes.<sup>[5](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366521.pdf)</sup>

Two SSE2 instructions bridge the MMX and XMM register files: MOVQ2DQ moves a quadword integer from an MMX source register to an XMM destination register, and MOVDQ2Q moves the low quadword from an XMM source register to an MMX destination register.<sup>[5](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366521.pdf)</sup> AMD's instruction reference lists the XMM-register variant of MOVD and the non-temporal store MOVNTI as members of the SSE2 subset, indicated by CPUID function 0000_0001h, EDX[26].<sup>[6](https://docs.amd.com/api/khub/documents/j44LvPXzuuXgM0WyHKQfeQ/content)</sup>

SSE2 also added cacheability control. The CLFLUSH (flush cache line) instruction, introduced with the SSE2 extensions, writes and invalidates the cache line associated with a specified linear address; the invalidation applies to all levels of the processor's cache hierarchy and is broadcast throughout the cache coherency domain.<sup>[5](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366521.pdf)</sup>

## Detection and operating system support

Software detects SSE2 through the CPUID instruction. After confirming that the processor implements CPUID, a program executes CPUID with EAX = 1 and tests bit 26 of the returned EDX feature flags; Intel's optimization manual gives the test value 00400000h for this bit.<sup>[10](https://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf)</sup> The canonical CPUID notation is CPUID.01H:EDX.SSE2[bit 26].<sup>[4](https://www.intel.com/content/www/us/en/developer/articles/technical/trusted-cpu-feature-detection-library-for-intel-software-guard-extensions-intel-sgx.html)</sup>

The operating system requirements for SSE2 support are the same as those for SSE: the OS must provide support for saving and restoring SSE state on context switches so that applications using these instructions behave consistently.<sup>[10](https://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf)</sup> On Windows, the IsProcessorFeaturePresent function reports SSE2 availability through the PF_XMMI64_INSTRUCTIONS_AVAILABLE constant (value 10), which is not supported on [Windows 2000](https://www.edgepedia.org/windows-2000).<sup>[11](https://learn.microsoft.com/en-us/windows/win32/api/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent)</sup>

## Baseline status in modern software

SSE2 has become a floor for 64-bit software. Microsoft's debugger documentation notes that the x64 instruction set includes additions to x86 such as SSE 2, and that programs compiled for x64 can freely use these instructions.<sup>[7](https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-instructions)</sup> Installing the 64-bit version of [Windows 10](https://www.edgepedia.org/windows-10) requires the processor to support SSE2, along with Physical Address Extension (PAE), No-eXecute (NX), and CMPXCHG16b; the installation wizard checks for these features and will not continue without them.<sup>[8](https://learn.microsoft.com/en-ie/answers/questions/bb1b471b-4575-4a52-ae91-10f124b69795/win-10-update?forum=windows-all)</sup> Consistent with this, the Microsoft C runtime's `_set_SSE2_enable` function, which toggles SSE2 implementations of math routines such as `atan`, `ceil`, `exp`, `floor`, `log`, and `log10` on 32-bit x86, is not available on x64 architectures because SSE2 is enabled by default there.<sup>[12](https://learn.microsoft.com/en-us/cpp/c-runtime-library/reference/set-sse2-enable?view=msvc-170)</sup>

Compiler and library toolchains treat SSE2 as a selectable baseline code path. AMD's AOCL libraries, for example, allow the environment variable `AOCL_ENABLE_INSTRUCTIONS` to be set to `SSE2`, `AVX`, `AVX2`, or `AVX512` to dispatch to an ISA-specific code path, with SSE2 the lowest optimized tier above the generic reference path.<sup>[13](https://docs.amd.com/r/en-US/57404-AOCL-user-guide/Instruction-Set-Selection)</sup>

## Intended applications

Intel describes SSE2 as enhancing processor performance for advanced 3-D graphics, video decoding and encoding, speech recognition, [E-commerce](https://www.edgepedia.org/e-commerce), Internet, scientific, and engineering applications.<sup>[3](https://www.intel.com/content/www/us/en/support/articles/000005779/processors.html)</sup> AMD's application-programming discussion of the SSE family, which includes SSE2, notes that the ability to operate in parallel on double-precision floating-point vector elements suits computations such as dense systems of linear equations, matrix and vector-space operations with real and complex numbers, and physical-modeling algorithms in professional CAD applications simulating heat transfer or fluid dynamics.<sup>[9](https://docs.amd.com/api/khub/documents/sfvvekC9mDflu6vd3R0NXA/content)</sup>

## Successors

SSE3 followed SSE2 and was introduced with Pentium 4 processors supporting Hyper-Threading Technology, built on the [90 nm process](https://www.edgepedia.org/90-nm-process); it offers 13 instructions that accelerate the performance of SSE, SSE2, and x87-FP math capabilities.<sup>[3](https://www.intel.com/content/www/us/en/support/articles/000005779/processors.html)</sup> Later legacy subsets (SSSE3, SSE4.1, and SSE4.2) and the extended AVX-family subsets built further on the model SSE2 established, with AVX512 supporting 512-bit vector operands.<sup>[9](https://docs.amd.com/api/khub/documents/sfvvekC9mDflu6vd3R0NXA/content)</sup>

## References

1. [Intel® 64 and IA-32 Architectures Software Developer's Manual, Section 17.7: Streaming SIMD Extensions 2 (SSE2)](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366821.pdf)
2. [Intel Announces New NetBurst® Micro-Architecture For Pentium® 4 Processor (press release, 2000)](https://www.intel.com/pressroom/archive/releases/2000/dp082200.htm)
3. [Intel® Instruction Set Extensions Technology](https://www.intel.com/content/www/us/en/support/articles/000005779/processors.html)
4. [Trusted CPU Feature Detection Library for Intel® Software Guard Extensions (Intel® SGX)](https://www.intel.com/content/www/us/en/developer/articles/technical/trusted-cpu-feature-detection-library-for-intel-software-guard-extensions-intel-sgx.html)
5. [Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1, Chapter 11: Programming with Streaming SIMD Extensions 2 (SSE2)](https://www.intel.com/content/dam/support/us/en/documents/processors/pentium4/sb/25366521.pdf)
6. [AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions](https://docs.amd.com/api/khub/documents/j44LvPXzuuXgM0WyHKQfeQ/content)
7. [x64 Instructions, Windows drivers, Microsoft Learn](https://learn.microsoft.com/en-us/windows-hardware/drivers/debugger/x64-instructions)
8. [Win 10 update, Microsoft Q&A (SSE2 among 64-bit Windows 10 CPU requirements)](https://learn.microsoft.com/en-ie/answers/questions/bb1b471b-4575-4a52-ae91-10f124b69795/win-10-update?forum=windows-all)
9. [AMD64 Architecture Programmer's Manual, Volume 1: Application Programming](https://docs.amd.com/api/khub/documents/sfvvekC9mDflu6vd3R0NXA/content)
10. [Intel® 64 and IA-32 Architectures Optimization Reference Manual, Chapter 4: Checking for SSE2 Support](https://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf)
11. [IsProcessorFeaturePresent function (processthreadsapi.h), Microsoft Learn](https://learn.microsoft.com/en-us/windows/win32/api/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent)
12. [_set_SSE2_enable, Microsoft Learn](https://learn.microsoft.com/en-us/cpp/c-runtime-library/reference/set-sse2-enable?view=msvc-170)
13. [Instruction Set Selection, AOCL User Guide (57404)](https://docs.amd.com/r/en-US/57404-AOCL-user-guide/Instruction-Set-Selection)

---
*Topic: Encyclopedia › Technology and the built world › Computing and digital systems › Computer hardware › Processors & processor engineering › Instruction set architectures › x86 ISA extensions*

*Initially written Sep 17, 2026 · Reviewed: Oct 15, 2026 · Edited: Oct 15, 2026 · Last review: Oct 15, 2026*

*Copyright 2026 EdgeChat AI, a subsidiary of Biostate AI.*

License: Edgepedia Community License 1.0, https://www.edgepedia.org/edgepedia/license