# Threshold voltage
**Threshold voltage** (symbol Vth, VT, or VGS(th)) is the gate-to-source voltage at which a MOSFET forms a conducting inversion channel between its source and drain and begins to turn on[1](https://toshiba.semicon-storage.com/us/semiconductor/knowledge/faq/mosfet_common/what-is-a-mosfet.html). Below this voltage the device carries essentially no drain current; above it, the channel conducts and the drain current grows with the gate overdrive, the amount by which VGS exceeds Vth[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). It is one of the most important parameters in both transistor design and circuit design, because it sets the switching point of the device and, exponentially, its off-state leakage.
| Key fact | Detail |
|---|---|
| Definition | The gate-to-source voltage at which an inversion layer forms and the MOSFET turns on; distinct from the thermal voltage of BJT theory (about 26 mV)[1](https://toshiba.semicon-storage.com/us/semiconductor/knowledge/faq/mosfet_common/what-is-a-mosfet.html) |
| Physics condition | Inversion is defined as the gate voltage at which the surface potential reaches twice the Fermi potential, \( V_{\mathrm{th}} = V_{\mathrm{G}}(\Phi_{\mathrm{S}} = 2\Phi_{\mathrm{B}}) \)[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html) |
| Worked value | For \( N_{\mathrm{a}} = 3 \times 10^{18}\,\mathrm{cm^{-3}} \), \( t_{\mathrm{ox}} = 2\,\mathrm{nm} \), an n+-poly gate on p-silicon gives \( V_{\mathrm{th}} = 0.53\,\mathrm{V} \)[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html) |
| Datasheet convention | Power MOSFET datasheets usually specify VGS(th) at a small fixed drain current, most often 250 µA; the NTMFS0D7N03CG specifies 1.3 to 2.2 V at ID = 280 µA[3](https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1480151/csd19537q3-spice-model-inquiries) • [4](https://www.onsemi.com/pdf/datasheet/ntmfs0d7n03cg-d.pdf) |
| Body effect | With source-to-body bias VSB, \( V_{\mathrm{T}} = V_{\mathrm{T0}} + \gamma\left(\sqrt{2\phi_{\mathrm{F}} + V_{\mathrm{SB}}} - \sqrt{2\phi_{\mathrm{F}}}\right) \); reverse body bias raises the threshold[5](https://ece-research.unm.edu/payman/classes/ECE321/lectures/lecture8.pdf) |
| Temperature coefficient | Threshold voltage falls with temperature; the NTMFS0D7N03CG lists −5.1 mV/°C, and a typical integrated-circuit value is about −1 mV/K[4](https://www.onsemi.com/pdf/datasheet/ntmfs0d7n03cg-d.pdf) • [2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html) |
| Design tradeoff | A lower Vth increases the overdrive and reduces gate delay, but exponentially increases subthreshold leakage current[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html) |
## Physical origin
The threshold voltage follows from the physics of the metal-oxide-semiconductor (MOS) capacitor. Sweeping the gate voltage of an n-channel device on a p-type substrate through four regimes: at the flatband voltage the silicon bands are flat; at zero gate voltage a depletion zone of immobile negative acceptor ions forms under the gate; as the gate rises further but stays below threshold, the depletion region deepens to its maximum width \( W_{\mathrm{dep}} \); and when the surface potential reaches twice the Fermi potential \( \Phi_{\mathrm{B}} \), a thin layer of free electrons, the inversion layer, appears directly under the gate oxide[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html).
The gate voltage minimally required to produce this inversion layer is the threshold voltage, and the standard long-channel expression is
The threshold voltage follows the formula below:
\[ V_{\mathrm{th}} = \Phi_{\mathrm{fb}} + 2\Phi_{\mathrm{B}} + \frac{\sqrt{2 q N_{\mathrm{a}} \varepsilon_{\mathrm{si}} \cdot 2 \Phi_{\mathrm{B}}}}{C'_{\mathrm{ox}}} \]
where \( \Phi_{\mathrm{fb}} \) is the flatband voltage (the gate-to-substrate work-function difference, adjusted for interface charge), \( N_{\mathrm{a}} \) is the substrate doping, \( \varepsilon_{\mathrm{si}} \) is the permittivity of silicon, and \( C'_{\mathrm{ox}} \) is the gate-oxide capacitance per unit area[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). The Fermi potential itself is \( \Phi_{\mathrm{B}} = (kT/q) \ln(N_{\mathrm{a}}/n_{\mathrm{i}}) \), so the threshold depends on doping, gate material, oxide thickness, and temperature[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). In the worked example above, the flatband term is −1.06 V, the \( 2\Phi_{\mathrm{B}} \) term is 1.0 V, and the depletion-charge term brings the total to 0.53 V[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html).
**Role in device operation.** Once the channel exists, the drain voltage selects the conduction mode. In the triode region, \( V_{\mathrm{DS}} \leq V_{\mathrm{GS}} - V_{\mathrm{th}} \), the device acts as a voltage-controlled resistor; in saturation, \( V_{\mathrm{DS}} > V_{\mathrm{GS}} - V_{\mathrm{th}} \), the channel pinches off at the drain and the current follows the square law \( I_{\mathrm{D}} = \tfrac{1}{2}\mu_{\mathrm{n}}C'_{\mathrm{ox}}(W/L)(V_{\mathrm{GS}} - V_{\mathrm{th}})^2 \)[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). The same threshold separates the three operating regions taught in introductory electronics: cutoff when \( V_{\mathrm{GS}} < V_{\mathrm{T}} \), triode, and saturation[6](https://engineering.ju.edu.jo/Laboratories/Electronics%20lab%20manual.pdf).
## Enhancement and depletion types
The sign and meaning of the threshold distinguish the two operating modes of a MOSFET. In an enhancement-type device, VGS = 0 V leaves the transistor off, so it is called normally off; the threshold is positive for an n-channel device and negative for a p-channel one. In a depletion-type device, a channel exists at zero gate bias, so it is normally on and is commanded off by an applied VGS[1](https://toshiba.semicon-storage.com/us/semiconductor/knowledge/faq/mosfet_common/what-is-a-mosfet.html). Most MOSFETs on the market are enhancement types, because in load-switch applications a device that conducts when a control signal fails low would create a safety problem[1](https://toshiba.semicon-storage.com/us/semiconductor/knowledge/faq/mosfet_common/what-is-a-mosfet.html).
Channel polarity matters as well: n-channel devices are enhanced when the gate is pulled positive with respect to the source, p-channel devices when the gate is pulled negative[7](https://www.microchip.com/en-us/products/power-management/discretes/mosfets/small-signal). Because electrons are more mobile than holes, an n-channel part of equal chip area has lower on-resistance and better characteristics than its p-channel counterpart[1](https://toshiba.semicon-storage.com/us/semiconductor/knowledge/faq/mosfet_common/what-is-a-mosfet.html).
## Body effect
When the body (substrate) terminal is not tied to the source, a source-to-body voltage VSB shifts the threshold. The standard expression is
\[ V_{\mathrm{T}} = V_{\mathrm{T0}} + \gamma\left(\sqrt{2\phi_{\mathrm{F}} + V_{\mathrm{SB}}} - \sqrt{2\phi_{\mathrm{F}}}\right) \]
where \( V_{\mathrm{T0}} \) is the zero-bias threshold, \( \gamma = \sqrt{2qN_{\mathrm{A}}\varepsilon_{\mathrm{si}}}/C_{\mathrm{ox}} \) is the body-effect coefficient, and \( \phi_{\mathrm{F}} \) is the Fermi potential of the substrate[5](https://ece-research.unm.edu/payman/classes/ECE321/lectures/lecture8.pdf) • [8](https://www.montana.edu/aolson/eele414/lecture_notes/eele414_module_02_MOSFETs.pdf). Reverse body bias widens the depletion region under the gate, so a larger gate voltage is needed to invert the surface and the threshold increases[9](https://web.mit.edu/course/6/6.012/SPR98/www/lectures/S98_Lecture9.pdf). In the UNM lecture example, \( V_{\mathrm{T0}} = 0.8\,\mathrm{V} \), \( \gamma = 0.6\,\mathrm{V^{1/2}} \), and \( \phi_{\mathrm{F}} = 0.4\,\mathrm{V} \) with \( V_{\mathrm{SB}} = 2.5\,\mathrm{V} \) give \( V_{\mathrm{T}} = 1.35\,\mathrm{V} \)[5](https://ece-research.unm.edu/payman/classes/ECE321/lectures/lecture8.pdf). Along the channel itself, the local channel-to-body voltage rises from source to drain, so the local threshold rises too, which further reduces the drain current compared with the ideal model[9](https://web.mit.edu/course/6/6.012/SPR98/www/lectures/S98_Lecture9.pdf).
## Short-channel effects: DIBL and roll-off
In devices with gate lengths below about 1 µm, the drain is close enough to the source that its voltage penetrates the channel electrostatically, lowering the source-to-channel energy barrier the gate is supposed to control. This drain-induced barrier lowering (DIBL) reduces the threshold voltage, with the decrease observed to be almost linear in VDS in improperly scaled devices[10](https://archive.nptel.ac.in/content/storage2/courses/117103066/chap2/slides/slide28.htm). A common model writes the shift as \( \Delta V_{\mathrm{th}} = -(V_{\mathrm{DS}} + 0.4\,\mathrm{V})\,e^{-L/l_{\mathrm{d}}} \), with a characteristic length \( l_{\mathrm{d}} \propto \sqrt[3]{t_{\mathrm{ox}} W_{\mathrm{dep}} X_{\mathrm{j}}} \) set by oxide thickness, depletion width, and junction depth[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). The related threshold roll-off with decreasing channel length means that \( V_{\mathrm{th}} \) is effectively a function of \( L \), \( W \), \( V_{\mathrm{DS}} \), and temperature, so devices match only when built with the same length[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). There is also a reverse short-channel effect, in which halo implants around source and drain raise \( V_{\mathrm{th}} \) as \( L \) shrinks[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html).
Because DIBL lowers the threshold at high drain bias, it raises off-state leakage; the countermeasures are structural. Ultra-thin-body silicon-on-insulator devices physically cap the depletion region, FinFETs wrap the gate around three sides of a fin, and nanosheet (gate-all-around) devices surround stacked channels completely, all improving gate electrostatic control and suppressing DIBL[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html).
## Measurement and datasheet meaning
Threshold voltage is a defined-at-a-current quantity, not a sharp physical boundary. For power MOSFETs, the standard test holds the device at a small, fixed drain bias (0.1 V in one university characterization procedure) and ramps the gate until the forward current exceeds a preset value, 1 mA in that procedure[11](https://research.ece.ncsu.edu/wp-content/uploads/sites/10/2019/07/etd22.pdf). Industry datasheets most often specify VGS(th) at ID = 250 µA[3](https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1480151/csd19537q3-spice-model-inquiries) • [12](https://community.infineon.com/t5/Knowledge-Base-Articles/Selecting-Provider-FET-for-VBUS-in-CCG3PA-Designs/ta-p/251794), and the IEC 63275-1:2022 reliability standard for SiC MOSFETs defines a threshold current for measuring Vth by constant-current and spot methods[13](https://standards.iteh.ai/catalog/standards/iec/83f29a65-aff3-48c8-b2e5-8c07c5eb3b12/iec-63275-1-2022).
**Threshold is not full turn-on.** The datasheet threshold marks where the FET just begins to conduct, not where it is fully enhanced. For TI's 80 V and 100 V FETs, the typical VGS(th) corresponds to ID = 250 µA, while RDS(on) is specified and tested only at VGS ≥ 6 V[3](https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1480151/csd19537q3-spice-model-inquiries). Designers therefore read the gate plateau voltage or the RDS(on) versus VGS plot to find the gate voltage at which the device is fully on; in [USB Power Delivery](https://www.edgepedia.org/usb-power-delivery) designs, a plateau voltage below 2.8 V is sought so the FET is completely enhanced at 3.2 V of gate drive[12](https://community.infineon.com/t5/Knowledge-Base-Articles/Selecting-Provider-FET-for-VBUS-in-CCG3PA-Designs/ta-p/251794).
## Temperature and variation
Threshold voltage falls as temperature rises, because more electrons are thermally excited into the conduction band[14](https://www.infineon.com/assets/row/public/documents/24/42/infineon-designing-with-power-mosfets-applicationnotes-en.pdf?fileId=8ac78c8c7ddc01d7017e6c619a490f47). The NTMFS0D7N03CG datasheet lists a threshold temperature coefficient of −5.1 mV/°C at ID = 280 µA[4](https://www.onsemi.com/pdf/datasheet/ntmfs0d7n03cg-d.pdf), and the 2N7000 datasheet's normalized curve shows VGS(th) falling from about 1.2 at −50 °C to about 0.67 at 150 °C while RDS(on) rises over the same range[15](https://ww1.microchip.com/downloads/en/DeviceDoc/2N7000-N-Channel-Enhancement-Mode-Vertical-DMOS-FET-Data-Sheet-20005695A.pdf). In integrated circuits, the temperature dependence is about −1 mV/K and process variation is on the order of ±50 mV; because leakage depends exponentially on the threshold, a shift of a hundred millivolts has a drastic effect, and this leakage limit is what stopped supply-voltage scaling below roughly 90 nm nodes[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). Statistical variation also arises from the random number and position of dopant atoms in the channel, a mechanism studied in bulk and SOI technologies[16](https://www.sciencedirect.com/science/article/pii/0038110192901556) • [17](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-37.pdf).
## Design tradeoff
The threshold voltage is the central knob in the speed-versus-leakage balance of CMOS design. A lower \( V_{\mathrm{th}} \) increases the overdrive when the transistor turns on and reduces gate delay, but it exponentially increases the leakage current through the subthreshold relation \( I_{\mathrm{leak}} = 100\,\mathrm{nA} \cdot (W/L)\,e^{-V_{\mathrm{th}}/(n V_{\mathrm{T}})} \)[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html). This exponential sensitivity, combined with temperature drift and process spread, is why supply and threshold scaling flattened near 1 V in advanced nodes[2](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html).
## References
1. [What is a MOSFET? Toshiba Electronic Devices & Storage](https://toshiba.semicon-storage.com/us/semiconductor/knowledge/faq/mosfet_common/what-is-a-mosfet.html)
2. [Design of Complex Integrated Circuits – The MOSFET, IIC-JKU](https://iic-jku.github.io/design-complex-ic/slides/mosfet.html)
3. [CSD19537Q3: Spice Model Inquiries, TI E2E support forum](https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1480151/csd19537q3-spice-model-inquiries)
4. [NTMFS0D7N03CG datasheet, onsemi](https://www.onsemi.com/pdf/datasheet/ntmfs0d7n03cg-d.pdf)
5. [ECE321 Lecture 8: MOSFET Threshold Voltage, University of New Mexico](https://ece-research.unm.edu/payman/classes/ECE321/lectures/lecture8.pdf)
6. [Electronics Lab Manual, Mechatronics Engineering, University of Jordan](https://engineering.ju.edu.jo/Laboratories/Electronics%20lab%20manual.pdf)
7. [Small-Signal MOSFETs, Microchip Technology](https://www.microchip.com/en-us/products/power-management/discretes/mosfets/small-signal)
8. [EELE414 Module 02: MOSFETs, Montana State University](https://www.montana.edu/aolson/eele414/lecture_notes/eele414_module_02_MOSFETs.pdf)
9. [6.012 Lecture 9: MOSFET Device Physics, MIT](https://web.mit.edu/course/6/6.012/SPR98/www/lectures/S98_Lecture9.pdf)
10. [Drain-Induced Barrier Lowering, NPTEL course slides](https://archive.nptel.ac.in/content/storage2/courses/117103066/chap2/slides/slide28.htm)
11. [Characterization of Power MOSFETs, NC State University thesis](https://research.ece.ncsu.edu/wp-content/uploads/sites/10/2019/07/etd22.pdf)
12. [Selecting Provider FET for VBUS in CCG3PA Designs, Infineon Knowledge Base](https://community.infineon.com/t5/Knowledge-Base-Articles/Selecting-Provider-FET-for-VBUS-in-CCG3PA-Designs/ta-p/251794)
13. [IEC 63275-1:2022, Reliability Test Method for SiC MOSFET Bias](https://standards.iteh.ai/catalog/standards/iec/83f29a65-aff3-48c8-b2e5-8c07c5eb3b12/iec-63275-1-2022)
14. [Designing with Power MOSFETs, Infineon Application Note](https://www.infineon.com/assets/row/public/documents/24/42/infineon-designing-with-power-mosfets-applicationnotes-en.pdf?fileId=8ac78c8c7ddc01d7017e6c619a490f47)
15. [2N7000 N-Channel Enhancement-Mode Vertical DMOS FET Data Sheet, Microchip](https://ww1.microchip.com/downloads/en/DeviceDoc/2N7000-N-Channel-Enhancement-Mode-Vertical-DMOS-FET-Data-Sheet-20005695A.pdf)
16. [Comparison of statistical variation of threshold voltage in bulk and SOI MOSFETs, ScienceDirect](https://www.sciencedirect.com/science/article/pii/0038110192901556)
17. [Threshold Voltage and DIBL Variability, UC Berkeley EECS-2015-37](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-37.pdf)
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