410 articles
Computer architecture
Computer architecture, also known as computing architecture, is the design of computer systems' organization and behavior, spanning instruction set architecture and microarchitecture, from x86 and ARM processors to pipelining and memory hierarchies.
Computer architecture simulator
A computer architecture simulator is a software program that models a processor, memory hierarchy, or whole computer system, letting researchers evaluate hardware designs before building them.
Computer cluster
A computer cluster is a set of connected computers, called nodes, managed as a single system for high availability or high performance computing, as in Google's Borg clusters.
Computer performance
Computer performance is the amount of useful work a computer system accomplishes per unit of time, measured as latency (time to finish a task) or throughput (tasks completed in a fixed time).
Constrained-random verification
Constrained-random verification (CRV) is a hardware design verification methodology in which a constraint solver generates random but legal test stimulus, and it underlies the standard UVM framework.
Control unit
The control unit (CU) is the part of a CPU that decodes instructions and generates control signals to direct the processor's operation, implemented in hardwired or microprogrammed form.
Counter (digital)
A digital counter is a sequential logic circuit built from flip-flops that steps through a prescribed sequence of states, usually binary, on each clock pulse.
CPU cache
A CPU cache is small, fast memory in a processor that holds copies of recently used data and instructions, arranged in L1, L2, and L3 levels.
CPU-Z
CPU-Z is a freeware system identification utility from CPUID that reports detailed processor, mainboard, memory, and graphics information, with a Windows version and an Android app with over 100 million installs.
CPUID
CPUID is an x86 processor instruction that returns identification and feature information about the CPU, introduced with the Intel Pentium in 1993 and used to discover processor capabilities at run time.
Cray-1
The Cray-1, also known as Cray I, was a vector supercomputer designed by Seymour Cray and sold by Cray Research from 1976, the first commercially successful vector processor.
Cyrix 6x86
The Cyrix 6x86, codenamed M1, was an x86 processor introduced by Cyrix in October 1995 as a pin-compatible Pentium competitor, matching it at lower clock speeds.
Data General Nova
The Data General Nova is a 16-bit minicomputer introduced by Data General in 1968 for under $10,000, the fastest minicomputer on the market for several years.
Data structure alignment
Data structure alignment, also called data alignment or memory alignment, is the requirement that data sit at addresses divisible by its size, with padding inserted by compilers.
Dataflow architecture
A dataflow architecture is a computer architecture in which instructions fire as soon as their operands are ready, rather than in the fixed order a program counter sets.
DEC Alpha
DEC Alpha, originally named Alpha AXP, is a 64-bit RISC computer architecture developed by Digital Equipment Corporation, announced in 1992 to replace the 32-bit VAX.
Dhrystone
Dhrystone is a small synthetic benchmark measuring integer performance of processors and compilers, created by Reinhold Weicker in 1984 and scored in DMIPS; it remains in use for embedded processors.
Difference engine
A difference engine, or difference machine, is a mechanical calculating machine that computes and prints polynomial tables using only repeated addition, designed by Charles Babbage from 1821.
Differential analyser
The differential analyser, or Bush differential analyzer, is a mechanical analog computer for solving differential equations, first built by Vannevar Bush at MIT in 1931.
Digital Equipment Corporation
Digital Equipment Corporation (DEC), marketed as Digital, was an American computer company founded in 1957 that became the world's second-largest computer company and leading minicomputer maker.
Digital signal processor
A digital signal processor, also called a DSP chip, is a specialized microprocessor whose architecture is optimized for real-time signal processing, notably single-cycle multiply-accumulate operations and filtering.
Direct memory access
Direct memory access (DMA) is a transfer strategy in which hardware moves data to or from memory without using the processor, freeing it for other tasks.
Directory-based coherence
Directory-based coherence is a cache coherence scheme for shared-memory multiprocessors in which a directory tracks which caches hold each memory block, letting writes go only to those caches instead of being broadcast, as in snooping systems.
Dynamic voltage and frequency scaling
Dynamic voltage and frequency scaling (DVFS) is a power management technique that adjusts a processor's supply voltage and clock frequency at runtime to match the current workload and save energy.
EDSAC
EDSAC, the Electronic Delay Storage Automatic Calculator, was an early stored-program computer built at the University of Cambridge under Maurice Wilkes, first run in May 1949.
Elbrus (microprocessor)
Elbrus (Эльбрус) is a family of Russian general-purpose microprocessors developed by MCST in Moscow on the proprietary E2K VLIW architecture, which runs x86 software through dynamic binary translation.
Endianness
Endianness, also called byte ordering, is the convention a computer architecture uses to arrange the bytes of a multi-byte value in memory, as big-endian or little-endian.
Epyc
AMD Epyc is a family of x86 server processors made by AMD for data center, cloud, and AI workloads, launched in 2017 and competing with Intel's Xeon.
False sharing
False sharing is a performance pathology in shared-memory parallel systems where processors use different variables that sit in the same cache line, causing needless coherence traffic.
Fault tolerance
Fault tolerance is the ability of a system to continue running correctly when components fail, achieved by building in redundancy so no single failure interrupts operation.